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DATA SHEET
MOS INTEGRATED CIRCUIT
PD784214,784215,784216,784214Y,784215Y,784216Y
16/8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The PD784214, 784215, and 784216 are products of the PD784216 Subseries in the 78K/IV Series. Besides a high-speed and high-performance CPU, these controllers have ROM, RAM, I/O ports, 8-bit resolution A/D and D/A converters, timer, serial interface, real-time output ports, and interrupt functions and various other peripheral hardware. The PD784214Y, 784215Y, and 784216Y are based on the PD784216 Subseries with the addition of a multimaster-supporting I2C bus interface. The PD78F4216 and 78F4216Y, products with a flash memory instead of a masked ROM used as internal ROM, as well as a variety of development tools are also available. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing.
PD784216, 784216Y Subseries User's Manual Hardware: U12015E
78K/IV Series User's Manual Instructions: U10905E
FEATURES
* 78K/IV Series * Inherits peripheral functions of PD78078Y Subseries * Minimum instruction execution time 160 ns (@ fXX = 12.5 MHz operation with main system clock) 61 s (@ fXT = 32.768 kHz operation with subsystem clock) * I/O port: 86 pins * Timer/counter:
* *
* Standby function HALT/STOP/IDLE mode In power-saving mode: subsystem clock) * Clock division function * Watch timer: 1 channel * Watchdog timer: 1 channel * Clock output function Selectable from fXX, fXX/2, fXX/22, fXX/23 , fXX/24, fXX/25, fXX/26, fXX/27 , fXT * Buzzer output function Selectable from fXX/210, fXX/211, fXX/212, fXX/213 * A/D converter: 8-bit resolution x 8 channels bus Note * D/A converter: 8-bit resolution x 2 channels * Supply voltage: VDD = 2.2 to 5.5 V I2C HALT/IDLE mode (with
16-bit timer/event counter x 1 unit 8-bit timer/event counter x 6 units
* Serial interface: 3 channels UART/IOE (3-wire serial I/O): 2 channels CSI (3-wire serial I/O, multi-master supported): 1 channel
Note
PD784216Y Subseries only.
Unless otherwise specified, the PD784216 is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U11725EJ2V0DS00 (2nd edition) Date Published February 2000 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1996,2000
PD784214,784215,784216,784214Y,784215Y,784216Y
APPLICATIONS
Cellular phones, PHS, cordless telephones, CD-ROM, AV equipment
ORDERING INFORMATION
Part Number Package Internal ROM (bytes) Internal RAM (bytes)
PD784214GC-xxx-8EU PD784214GF-xxx-3BA PD784215GC-xxx-8EU PD784215GF-xxx-3BA PD784216GC-xxx-8EU PD784216GF-xxx-3BA
100-pin plastic LQFP (fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic LQFP (fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic LQFP (fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm)
96 K 96 K 128 K 128 K 128 K 128 K 96 K 96 K 128 K 128 K 128 K 128 K
3584 3584 5120 5120 8192 8192 3584 3584 5120 5120 8192 8192
PD784214YGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 x 14 mm) PD784214YGF-xxx-3BA 100-pin plastic QFP (14 x 20 mm) PD784215YGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 x 14 mm) PD784215YGF-xxx-3BA 100-pin plastic QFP (14 x 20 mm) PD784216YGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 x 14 mm) PD784216YGF-xxx-3BA 100-pin plastic QFP (14 x 20 mm)
Remark xxx indicates ROM code suffix.
2
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
78K/IV SERIES LINEUP
: Under mass production : Under development I2C bus supported Multi-master I2C bus supported
PD784038Y PD784038
PD784225Y PD784225
80-pin, ROM correction added Multi-master I2C bus supported
Standard models
PD784026
Enhanced A/D converter, 16-bit timer, and power management
Enhanced internal memory capacity Pin-compatible with the PD784026 Multi-master I2C bus supported
PD784216Y PD784216
100-pin, enhanced I/O and internal memory capacity
PD784218Y PD784218
Enhanced internal memory capacity, ROM correction added
PD784054 PD784046
ASSP models
PD784956A
For D/A inverter control
On-chip 10-bit A/D converter
PD784938
Enhanced functions of the PD784908, enhanced internal memory capacity, ROM correction added. Multi-master I2C bus supported
PD784908
On-chip IEBusTM controller
PD784928Y PD784915
Software servo control On-chip analog circuit for VCRs Enhanced timer
PD784928
Enhanced functions of the PD784915
PD784967
On-chip FTP controller/driver
Data Sheet U11725EJ2V0DS00
3
PD784214,784215,784216,784214Y,784215Y,784216Y
FUNCTIONS (1/2)
Part Number Item Number of basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space I/O port Total CMOS input CMOS I/O N-ch open-drain I/O Pins with ancillary Pins with pull-up resistor ROM RAM 113 8 bits x 16 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory mapping) * 160 ns/320 ns/640 ns/1280 ns/2560 ns (@ fXX = 12.5-MHz operation with main system clock) * 61 s (@ fXT = 32.768-kHz operation with subsystem clock) 96 Kbytes 3584 bytes 128 Kbytes 5120 bytes 8192 bytes
PD784214, PD784214Y
PD784215, PD784215Y
PD784216, PD784216Y
1 Mbytes with program and data spaces combined 86 8 72 6 70 22 6 4 bits x 2, or 8 bits x 1 Timer/event counter: (16-bit) Timer counter x 1 Capture/compare register x 2 Pulse output * PPG output * Square wave output * One-shot pulse output Pulse output * PWM output * Square wave output Pulse output * PWM output * Square wave output Pulse output * PWM output * Square wave output Pulse output * PWM output * Square wave output Pulse output * PWM output * Square wave output Pulse output * PWM output * Square wave output
functions Note LED direct drive output Middlevoltage pin Real-time output port Timer/counter
Timer/event counter 1: (8-bit) Timer/event counter 2: (8-bit) Timer/event counter 5: (8-bit) Timer/event counter 6: (8-bit) Timer/event counter 7: (8-bit) Timer/event counter 8: (8-bit)
Timer counter x 1 Compare register x 1 Timer counter x 1 Compare register x 1 Timer counter x 1 Compare register x 1 Timer counter x 1 Compare register x 1 Timer counter x 1 Compare register x 1 Timer counter x 1 Compare register x 1
Note The pins with ancillary functions are included in the I/O pins.
4
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
FUNCTIONS (2/2)
Part Number Item Serial interface A/D converter D/A converter Clock output Buzzer output Watch timer Watchdog timer Standby Interrupt Hardware source Software source Non-maskable Maskable
PD784214, PD784214Y
PD784215, PD784215Y
PD784216, PD784216Y
* UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator) * CSI (3-wire serial I/O, multi-master I2C bus supportedNote): 1 channel 8-bit resolution x 8 channels 8-bit resolution x 2 channels Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT Selectable from fXX/210, fXX/211, fXX/212, fXX/213 1 channel 1 channel * HALT/STOP/IDLE modes * In low-power consumption mode (with subsystem clock): HALT/IDLE mode 29 (internal: 20, external: 9) BRK instruction, BRKCS instruction, operand error Internal: 1, external: 1 Internal: 19, external: 8 * 4 programmable priority levels * 3 service modes: vectored interrupt/macro service/context switching
Supply voltage Package
VDD = 2.2 to 5.5 V 100-pin plastic LQFP (fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm)
Note PD784216Y Subseries only.
Data Sheet U11725EJ2V0DS00
5
PD784214,784215,784216,784214Y,784215Y,784216Y
CONTENTS
1. DIFFERENCES AMONG MODELS IN PD784216, 784216Y SUBSERIES ............................... 2. MAJOR DIFFERENCES FROM PD78078, 78078Y SUBSERIES ..............................................
8 9
3. PIN CONFIGURATION (Top View) ................................................................................................ 10 4. BLOCK DIAGRAM .......................................................................................................................... 13 5. PIN FUNCTION ............................................................................................................................... 14 5.1 Port Pins ................................................................................................................................ 14 5.2 Non-port Pins ....................................................................................................................... 16 5.3 Pin I/O Circuits and Recommended Connections of Unused Pins .............................. 18 6. CPU ARCHITECTURE .................................................................................................................... 22 6.1 Memory Space ...................................................................................................................... 22 6.2 CPU Registers ...................................................................................................................... 26
6.2.1 General-purpose registers .......................................................................................................... 6.2.2 Control registers .......................................................................................................................... 6.2.3 Special function registers (SFRs) ............................................................................................... 26 27 28
7. PERIPHERAL HARDWARE FUNCTIONS ..................................................................................... 7.1 Ports ....................................................................................................................................... 7.2 Clock Generation Circuit ..................................................................................................... 7.3 Real-Time Output Port ......................................................................................................... 7.4 Timer/Event Counter ............................................................................................................ 7.5 A/D Converter ....................................................................................................................... 7.6 D/A Converter ....................................................................................................................... 7.7 Serial Interface .....................................................................................................................
7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) .................................................... 7.7.2 Clocked serial interface (CSI) .....................................................................................................
33 33 34 36 37 39 40 41
42 44
7.8 7.9 7.10 7.11 7.12
Clock Output Function ........................................................................................................ Buzzer Output Function ...................................................................................................... Edge Detection Function .................................................................................................... Watch Timer .......................................................................................................................... Watchdog Timer ....................................................................................................................
45 46 46 46 47 48 48 50 51 51 52
8. INTERRUPT FUNCTION ................................................................................................................. 8.1 Interrupt Sources ................................................................................................................. 8.2 Vectored Interrupt ................................................................................................................ 8.3 Context Switching ................................................................................................................ 8.4 Macro Service ....................................................................................................................... 8.5 Application Example of Macro Service .............................................................................
6
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
9. LOCAL BUS INTERFACE .............................................................................................................. 53 9.1 Memory Expansion .............................................................................................................. 54 9.2 Programmable Wait .............................................................................................................. 54 10. STANDBY FUNCTION .................................................................................................................... 55 11. RESET FUNCTION ......................................................................................................................... 57 12. INSTRUCTION SET ........................................................................................................................ 58 13. ELECTRICAL SPECIFICATIONS .................................................................................................. 63 14. PACKAGE DRAWINGS ................................................................................................................... 82 15. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 84 APPENDIX A DEVELOPMENT TOOLS .............................................................................................. 85 APPENDIX B. RELATED DOCUMENTS ............................................................................................. 88
Data Sheet U11725EJ2V0DS00
7
PD784214,784215,784216,784214Y,784215Y,784216Y
1. DIFFERENCES AMONG MODELS IN PD784216, 784216Y SUBSERIES
The only difference among the PD784214, 784215, and 784216 lies in the internal memory capacity. The PD784214Y, 784215Y, and 784216Y are based on the PD78424, 784215, and 784216 with an I2C bus control function added. The PD78F4216 and 78F4216Y are provided with a 128-Kbyte flash memory instead of the mask ROM of the above models. These differences are summarized in Table 1-1. Table 1-1. Differences among Models in PD784216 and 784216Y Subseries
Part Number Item Internal ROM
PD784214, PD784214Y
96 Kbytes (mask ROM) 3584 bytes None
PD784215, PD784215Y
128 Kbytes (mask ROM) 5120 bytes
PD784216, PD784216Y
PD78F4216, PD78F4216Y
128 Kbytes (Flash memory)
Internal RAM Internal memory size switching register (IMS) Supply voltage Electrical specifications Recommended soldering conditions TEST pin VPP pin
8192 bytes Provided Note
VDD = 2.2 to 5.5 V Refer to the Data Sheet for each device.
VDD = 2.7 to 5.5 V
Provided None
None Provided
Note Internal flash memory capacity and internal RAM capacity can be changed using the internal memory size switching register (IMS). Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (not engineering samples) of the mask ROM version.
8
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
2. MAJOR DIFFERENCES FROM PD78078, 78078Y SUBSERIES
Series Name Item CPU Minimum instruction execution time With main system clock With subsystem clock Memory space I/O port Total CMOS input CMOS I/O N-ch open-drain I/O Pins with ancillary functions Note 1 Pins with pull-up resistor LED direct drive output Middle-voltage pin Timer/counter 16-bit CPU 160 ns (@ 12.5-MHz operation) 61 s (@ 32.768-kHz operation) 8-bit CPU 400 ns (@ 5.0-MHz operation) 122 s (@ 32.768-kHz operation)
PD784216, 784216Y Subseries
PD78078, 78078Y Subseries
1 Mbytes 86 8 72 6 70
64 Kbytes 88 2 78 8 86
22
16
6 * 16-bit timer/event counter x 1 unit * 8-bit timer/event counter x 6 units
8 * 16-bit timer/event counter x 1 unit * 8-bit timer/event counter x 4 units * UART/IOE (3-wire serial I/O) x 1 channel * CSI (3-wire serial I/O, 2-wire serial I/O, I2C busNote 3) x 1 channel * CSI (3-wire serial I/O, 3-wire serial I/O with automatic transmit/receive function) x 1 channel None None None None HALT/STOP modes
Serial interface
* UART/IOE (3-wire serial I/O) x 2 channels * CSI (3-wire serial I/O, multi-master I2C bus supportedNote 2) x 1 channel
Interrupt
NMI pin Macro service Context switching Programmable priority
Provided Provided Provided 4 levels HALT/STOP/IDLE modes In low-power consumption mode: HALT/IDLE modes * 100-pin plastic LQFP (fine pitch) (14 x 14 mm) * 100-pin plastic QFP (14 x 20 mm)
Standby function
Package
* 100-pin plastic LQFP (fine pitch) (14 x 14 mm) * 100-pin plastic QFP (14 x 20 mm) * 100-pin ceramic WQFN (14 x 20 mm) (PD78P078Y only)
Notes 1. The pins with ancillary functions are included in the I/O pins. 2. PD784216Y Subseries only 3. PD78078Y Subseries only
Data Sheet U11725EJ2V0DS00
9
PD784214,784215,784216,784214Y,784215Y,784216Y
3. PIN CONFIGURATION (Top View)
* 100-pin plastic LQFP (fine pitch) (14 x 14 mm)
PD784214GC-xxx-8EU, 784214YGC-xxx-8EU, PD784215GC-xxx-8EU, 784215YGC-xxx-8EU, PD784216GC-xxx-8EU, 784216YGC-xxx-8EU
P95 P94 P93 P92 P91 P90 TESTNote 1 P37 P36/TI01 P35/TI00 P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P103/TI8/TO8 P102/TI7/TO7 P101/TI6/TO6 P100/TI5/TO5 VDD P67/ASTB P66/WAIT P65/WR P64/RD P63/A19
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P120/RTP0 P121/RTP1 P122/RTP2 P123/RTP3 P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 VDD X2 X1 VSS XT2 XT1 RESET P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 AVDDNote 2 AVREF0 P10/ANI0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P62/A18 P61/A17 P60/A16 VSS P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P87/A7 P86/A6 P85/A5 P84/A4 P83/A3
Notes 1. Connect the TEST pin to VSS directly or via a pull-down resistor. For the pull-down connection, use a resistor with a resistance ranging from 470 to 10 k. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. 4. The SCL0 and SDA0 pins are available in PD784216Y Subseries products only.
10
P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVSSNote 3 P130/ANO0 P131/ANO1 AVREF1 P70/RxD2/SI2 P71/TxD2/SO2 P72/ASCK2/SCK2 P20/RxD1/SI1 P21/TxD1/SO1 P22/ASCK1/SCK1 P23/PCL P24/BUZ P25/SI0/SDA0Note 4 P26/SO0 P27/SCK0/SCL0Note 4 P80/A0 P81/A1 P82/A2
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
* 100-pin plastic QFP (14 x 20 mm)
PD784214GF-xxx-3BA, 784214YGF-xxx-3BA, PD784215GF-xxx-3BA, 784215YGF-xxx-3BA, PD784216GF-xxx-3BA, 784216YGF-xxx-3BA
P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P87/A7 P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P86/A6 P85/A5
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P60/A16 P61/A17 P62/A18 P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB VDD P100/TI5/TO5 P101/TI6/TO6 P102/TI7/TO7 P103/TI8/TO8 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/TI00 P36/TI01 P37 TESTNote 1 P90 P91 P92 P93 P94 P95 P120/RTP0 P121/RTP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 P84/A4 P83/A3 P82/A2 P81/A1 P80/A0 P27/SCK0/SCL0Note 4 P26/SO0 P25/SI0/SDA0Note 4 P24/BUZ P23/PCL P22/ASCK1/SCK1 P21/TxD1/SO1 P20/RxD1/SI1 P72/ASCK2/SCK2 P71/TxD2/SO2 P70/RxD2/SI2 AVREF1 P131/ANO1 P130/ANO0 AVSSNote 3 P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVREF0 AVDDNote 2
51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS
P02/INTP2/NMI P03/INTP3
RESET P00/INTP0 P01/INTP1
P04/INTP4 P05/INTP5
P122/RTP2 P123/RTP3 P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 VDD
Notes 1. Connect the TEST pin to VSS directly or via a pull-down resistor. For the pull-down connection, use a resistor with a resistance ranging from 470 to 10 k. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. 4. The SCL0 and SDA0 pins are available in PD784216Y Subseries products only.
Data Sheet U11725EJ2V0DS00
P06/INTP6
XT2 XT1
X2 X1
VSS
11
PD784214,784215,784216,784214Y,784215Y,784216Y
A0 to A19: AD0 to AD7: ANI0 to ANI7: ANO0, ANO1: ASCK1, ASCK2: ASTB: AVDD: AVREF0, AVREF1: AVSS: BUZ: INTP0 to INTP6: NMI: P00 to P06: P10 to P17: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P67: P70 to P72: P80 to P87: P90 to P95: P100 to P103: P120 to P127: Address Bus Address/Data Bus Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Buzzer Clock Interrupt from Peripherals Non-maskable Interrupt Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port8 Port9 Port10 Port12 P130, P131: PCL: RD: RESET: RTP0 to RTP7: RxD1, RxD2: SCK0 to SCK2: SCL0Note: SDA0Note: SI0 to SI2: SO0 to SO2: TEST: TI00, TI01, TI1, TI2, TI5 to TI8: TxD1, TxD2: VDD: VSS: WAIT: WR: X1, X2: XT1, XT2: Timer Input Transmit Data Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock) TO0 to TO2, TO5 to TO8: Timer Output Port13 Programmable Clock Read Strobe Reset Real-time Output Port Receive Data Serial Clock Serial Clock Serial Data Serial Input Serial Output Test
Note The SCL0 and SDA0 pins are available in PD784216Y Subseries only.
12
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
4. BLOCK DIAGRAM
INTP2/NMI INTP0, INTP1, INTP3 to INTP6 TI00 TI01 TO0 TI1 TO1 TI2 TO2
PROGRAMMABLE INTERRUPT CONTROLLER TIMER/EVENT COUNTER (16 BITS) TIMER/EVENT COUNTER1 (8 BITS) TIMER/EVENT COUNTER2 (8 BITS) TIMER/EVENT COUNTER5 (8 BITS) TIMER/EVENT COUNTER6 (8 BITS) TIMER/EVENT COUNTER7 (8 BITS) TIMER/EVENT COUNTER8 (8 BITS) WATCH TIMER RAM 78K/IV CPU CORE
UART/IOE1 BAUD-RATE GENERATOR UART/IOE2 BAUD-RATE GENERATOR CLOCKED SERIAL INTERFACE
RxD1/SI1 TxD1/SO1 ASCK1/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SI0/SDA0Note SO0 SCK0/SCL0Note AD0 to AD7 A0 to A7 A8 to A15
TI5/TO5
BUS I/F
A16 to A19 RD WR WAIT ASTB
TI6/TO6
ROM PORT0 PORT1 PORT2 PORT3 PORT4 PORT5
P00 to P06 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P80 to P87 P90 to P95 P100 to P103 P120 to P127 P130,P131 RESET X1
TI7/TO7
TI8/TO8
WATCHDOG TIMER
PORT6 PORT7
RTP0 to RTP7 NMI/INTP2 ANO0 ANO1 AVREF1 AVSS ANI0 to ANI7 AVREF0 AVDD AVSS P03 PCL
REAL-TIME OUTPUT PORT
PORT8 PORT9
D/A CONVERTER
PORT10 PORT12 PORT13
A/D CONVERTER SYSTEM CONTROL CLOCK OUTPUT CONTROL BUZZER OUTPUT
X2 XT1 XT2
BUZ
VDD VSS TEST
Note The SCL0 and SDA0 pins are available in PD784216Y Subseries only. This function supports the I2C bus interface. Remark The internal ROM and RAM capacities differ depending on the product.
Data Sheet U11725EJ2V0DS00
13
PD784214,784215,784216,784214Y,784215Y,784216Y
5. PIN FUNCTION 5.1 Port Pins (1/2)
Pin Name P00 P01 P02 P03 P04 P05 P06 P10 to P17 Input I/O I/O Alternate Function INTP0 INTP1 INTP2/NMI INTP3 INTP4 INTP5 INTP6 ANI0 to ANI7 Port 1 (P1): * 8-bit input port Port 2 (P2): * 8-bit I/O port * Input/output can be specified in 1-bit units. * Whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. Function Port 0 (P0): * 7-bit I/O port * Input/output can be specified in 1-bit units. * Whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software.
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47
I/O
RxD1/SI1 TxD1/SO1 ASCK1/SCK1 PCL BUZ SI0/SDA0Note SO0 SCK0/SCL0Note
I/O
TO0 TO1 TO2 TI1 TI2 TI00 TI01 --
Port 3 (P3): * 8-bit I/O port * Input/output can be specified in 1-bit units. * Whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software.
I/O
AD0 to AD7
Port 4 (P4): * 8-bit I/O port * Input/output can be specified in 1-bit units. * All pins set in input mode can be connected to on-chip pull-up resistors by means of software. * Can drive LEDs. Port 5 (P5): * 8-bit I/O port * Input/output can be specified in 1-bit units. * All pins set in input mode can be connected to on-chip pull-up resistors by means of software. * Can drive LEDs.
P50 to P57
I/O
A8 to A15
Note The SCL0 and SDA0 pins are available in PD784216Y Subseries only.
14
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
5.1 Port Pins (2/2)
Pin Name P60 P61 P62 P63 P64 P65 P66 P67 P70 I/O I/O I/O Alternate Function A16 A17 A18 A19 RD WR WAIT ASTB RxD2/SI2 Port 7 (P7): * 3-bit I/O port * Input/output can be specified in 1-bit units. * Whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. Function Port 6 (P6): * 8-bit I/O port * Input/output can be specified in 1-bit units. * All pins set in input mode can be connected to on-chip pull-up resistors by means of software.
P71
TxD2/SO2
P72
ASCK2/SCK2
P80 to P87
I/O
A0 to A7
Port 8 (P8): * 8-bit I/O port * Input/output can be specified in 1-bit units. * Whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. * Interrupt control flag (KRIF) is set to 1 when falling edge is detected at a pin of this port. -- Port 9 (P9): * N-ch open-drain middle-voltage I/O port * 6-bit I/O port * Input/output can be specified in 1-bit units. * Can directly drive LEDs. Port 10 (P10): * 4-bit I/O port * Input/output can be specified in 1-bit units. * Whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. Port 12 (P12): * 8-bit I/O port * Input/output can be specified in 1-bit units. * Whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. Port 13 (P13): * 2-bit I/O port * Input/output can be specified in 1-bit units.
P90 to P95
I/O
P100 P101 P102 P103 P120 to P127
I/O
TI5/TO5 TI6/TO6 TI7/TO7 TI8/TO8
I/O
RTP0 to RTP7
P130, P131
I/O
ANO0, ANO1
Data Sheet U11725EJ2V0DS00
15
PD784214,784215,784216,784214Y,784215Y,784216Y
5.2 Non-port Pins (1/2)
Pin Name TI00 TI01 TI1 TI2 TI5 TI6 TI7 TI8 TO0 TO1 TO2 TO5 TO6 TO7 TO8 RxD1 RxD2 TxD1 TxD2 ASCK1 ASCK2 SI0 SI1 SI2 SO0 SO1 SO2 SDA0Note SCK0 SCK1 SCK2 SCL0Note NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 Input I/O Output Input Input Output Input Output I/O Input Alternate Function P35 P36 P33 P34 P100/TO5 P101/TO6 P102/TO7 P103/TO8 P30 P31 P32 P100/TI5 P101/TI6 P102/TI7 P103/TI8 P20/SI1 P70/SI2 P21/SO1 P71/SO2 P22/SCK1 P72/SCK2 P25/SDA0 P20/RxD1 P70/RxD2 P26 P21/TxD1 P71/TxD2 P25/SI0 P27 P22/ASCK1 P72/ASCK2 P27/SCK0 P02/INTP2 P00 P01 P02/NMI P03 P04 P05 P06 Serial data input (UART1) Serial data input (UART2) Serial data output (UART1) Serial data output (UART2) Baud rate clock input (UART1) Baud rate clock input (UART2) Serial data input (3-wire serial clock I/O0) Serial data input (3-wire serial clock I/O1) Serial data input (3-wire serial clock I/O2) Serial data output (3-wire serial I/O0) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial data input/output (I2C bus) Serial clock input/output (3-wire serial I/O0) Serial clock input/output (3-wire serial I/O1) Serial clock input/output (3-wire serial I/O2) Serial data input/output (I2C bus) Non-maskable interrupt request input External interrupt request input Function External count clock input to 16-bit timer counter Capture trigger signal input to capture/compare register 00 External count clock input to 8-bit timer counter 1 External count clock input to 8-bit timer counter 2 External count clock input to 8-bit timer counter 5 External count clock input to 8-bit timer counter 6 External count clock input to 8-bit timer counter 7 External count clock input to 8-bit timer counter 8 16-bit timer output (shared by 14-bit PWM output) 8-bit timer output (shared by 8-bit PWM output)
Note PD784216Y Subseries only.
16
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
5.2 Non-port Pins (2/2)
Pin Name PCL BUZ RTP0 to RTP7 I/O Output Output Output Alternate Function P23 P24 P120 to P127 Function Clock output (for trimming main system clock and subsystem clock) Buzzer output Real-time output port that outputs data in synchronization with trigger Lower address/data bus for expanding memory externally Lower address bus for expanding memory externally Middle address bus for expanding memory externally Higher address bus for expanding memory externally Strobe signal output for read operation of external memory Strobe signal output for write operation of external memory To insert wait state(s) when external memory is accessed Strobe output to externally latch address information output to ports 4 through 6 and port 8 to access external memory -- -- System reset input Crystal connection for main system clock oscillation
AD0 to AD7 A0 to A7 A8 to A15 A16 to A19 RD WR WAIT ASTB
I/O Output
P40 to P47 P80 to P87 P50 to P57 P60 to P63
Output
P64 P65
Input Output
P66 P67
RESET X1 X2 XT1 XT2 ANI0 to ANI7 ANO0, ANO1 AVREF0 AVREF1 AVDD AVSS VDD VSS TEST
Input Input -- Input -- Input Output --
--
Crystal connection for subsystem clock oscillation
P10 to P17 P130, P131 --
Analog voltage input for A/D converter Analog voltage output for D/A converter To apply reference voltage for A/D converter To apply reference voltage for D/A converter Positive power supply for A/D converter. Connect to VDD. GND for A/D converter and D/A converter. Connect to VSS. Positive power supply GND Connect the TEST pin to VSS directly or via a pull-down resistor (this pin is for IC test). For the pull-down connection, use a resistor with a resistance ranging from 470 to 10 k.
Data Sheet U11725EJ2V0DS00
17
PD784214,784215,784216,784214Y,784215Y,784216Y
5.3 Pin I/O Circuits and Recommended Connections of Unused Pins
The input/output circuit type of each pin and recommended connections of unused pins are shown in Table 5-1. For each type of input/output circuit, refer to Figure 5-1. Table 5-1. Type of Pin Input/Output Circuits and Recommended Connections of Unused Pins (1/2)
Pin Name P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 to P06/INTP6 P10/ANI0 to P17/ANI7 P20/RxD1/SI1 P21/TxD1/SO1 P22/ASCK1/SCK1 P23/PCL P24/BUZ P25/SDA0Note/SI0 P26/SO0 P27/SCL0Note/SCK0 P30/TO0 to P32/TO2 P33/TI1, P34/TI2 P35/TI00, P36/TI01 P37 P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB P70/RxD2/SI2 P71/TxD2/SO2 P72/ASCK2/SCK2 P80/A0 to P87/A7 P90 to P95 P100/TI5/TO5 P101/TI6/TO6 P102/TI7/TO7 P103/TI8/TO8 P120/RTP0 to P127/RTP7 P130/ANO0, P131/ANO1 12-E 12-F 8-N 10-M 8-N 12-E 13-D 8-N 10-K 10-L 10-K 12-E 8-N 10-M 12-E 5-A 9 10-K 10-L 10-K 10-L Input I/O Connect to VSS or VDD Input: Independently connect to VSS via a resistor I/O Circuit Type 8-N I/O I/O Input: Recommended Connections of Unused Pins Independently connect to VSS via a resistor
Output: Leave open
Output: Leave open
Note The SCL0 and SDA0 pins are available in PD784216Y Subseries only.
18
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
Table 5-1. Types of Pin Input/Output Circuits and Recommended Connections of Unused Pins (2/2)
Pin Name RESET XT1 XT2 AVREF0 AVREF1 AVDD AVSS TEST Connect to VSS Connect the TEST pin to VSS directly or via a pull-down resistor. For the pull-down connection, use a resistor with a resistance ranging from 470 to 10 k. -- I/O Circuit Type 2-G 16 -- I/O Input Connect to VSS Leave open Connect to VSS Connect to VDD Recommended Connections of Unused Pins --
Remark Because the circuit type numbers are standardized among the 78K Series products, they are not sequential in some models (i.e., some circuits are not provided).
Data Sheet U11725EJ2V0DS00
19
PD784214,784215,784216,784214Y,784215Y,784216Y
Figure 5-1. Types of Pin I/O Circuits (1/2)
Type 2-G
Type 10-K
VDD
Pullup enable IN Data Schmitt trigger input with hysteresis characteristics VDD P-ch
P-ch
IN/OUT Open drain Output disable N-ch
Type 5-A
VDD
Type 10-L
VDD
Pullup enable VDD Data P-ch
P-ch
Pullup enable VDD Data IN/OUT P-ch
P-ch
IN/OUT Open drain Output disable VSS N-ch
Output disable
N-ch
Input enable Type 8-N VDD Type 10-M VDD
Pullup enable VDD Data P-ch
P-ch
Pullup enable VDD Data IN/OUT P-ch
P-ch
IN/OUT Output disable VSS N-ch
Output disable
N-ch
Type 9
Type 12-E
VDD
IN
P-ch N-ch
Comparator
+ -
Pullup enable VDD Data P-ch
P-ch
VREF (Threshold voltage)
IN/OUT Output disable Input enable Input enable P-ch Analog output voltage N-ch
N-ch
20
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
Figure 5-1. Types of Pin I/O Circuits (2/2)
Type 12-F VDD Data P-ch IN/OUT Output disable Input enable Analog output voltage N-ch VSS P-ch N-ch VSS
Type 16 Feedback cut-off P-ch
XT1
XT2
Type 13-D IN/OUT Data Output disable N-ch VDD
RD
P-ch
Middle-voltage output buffer
Data Sheet U11725EJ2V0DS00
21
PD784214,784215,784216,784214Y,784215Y,784216Y
6. CPU ARCHITECTURE 6.1 Memory Space
A memory space of 1 Mbyte can be accessed. Mapping of the internal data area (special function registers and internal RAM) can be specified by the LOCATION instruction. The LOCATION instruction must be always executed after reset cancellation, and must not be used more than once. (1) When LOCATION 0H instruction is executed * Internal memory The internal data area and internal ROM area are mapped as follows:
Part Number Internal Data Area 0F100H to 0FFFFH Internal ROM Area 00000H to 0F0FFH 10000H to 17FFFH 00000H to 0EAFFH 10000H to 1FFFFH 00000H to 0DEFFH 10000H to 1FFFFH
PD784214, PD784214Y PD784215, PD784215Y PD784216, PD784216Y
0EB00H to 0FFFFH
0DF00H to 0FFFFH
Caution
The following areas that overlap the internal data area of the internal ROM cannot be used when the LOCATION 0 instruction is executed.
Part Number Unusable Area 0F100H to 0FFFFH (3840 bytes)
PD784214, PD784214Y PD784215, PD784215Y PD784216, PD784216Y
0EB00H to 0FFFFH (5376 bytes)
0DF00H to 0FFFFH (8448 bytes)
* External memory The external memory is accessed in external memory expansion mode. (2) When LOCATION 0FH instruction is executed * Internal memory The internal data area and internal ROM area are mapped as follows:
Part Number Internal Data Area FF100H to FFFFFH Internal ROM Area 00000H to 17FFFH
PD784214, PD784214Y PD784215, PD784215Y PD784216, PD784216Y
FEB00H to FFFFFH
00000H to 1FFFFH
FDF00H to FFFFFH
00000H to 1FFFFH
* External memory The external memory is accessed in external memory expansion mode.
22
Data Sheet U11725EJ2V0DS00
Figure 6-1. Memory Map of PD784214, 784214Y
On execution of LOCATION 0H instruction
F F F F FH
On execution of LOCATION 0FH instruction
F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH
function registers (SFR) (256 bytes)
0 FEF FH
F FEF FH
External memory (928 Kbytes)
1 8 0 0 0H 1 7 F F FH 1 0 0 0 0H 0 F F F FH Special 0 F FDFH Note 1 0 F FD0H 0 FF 0 0H 0 FEF FH
Note 1
General-purpose registers (128 bytes)
0 FE8 0H 0 FE 7 FH FFE8 0H F FE 7 FH FF 1 0 0H F F 0 F FH
Internal RAM (3584 bytes)
PD784214,784215,784216,784214Y,784215Y,784216Y
Internal ROM (32768 bytes)
function registers (SFR) (256 bytes)
0 F E 3 BH 0 FE0 6H
Macro service control word area (54 bytes) Data area (512 bytes)
F F E 3 BH FFE0 6H
Data Sheet U11725EJ2V0DS00
0 FD0 0H 0 FCF FH
F FD0 0H F FCF FH
Internal RAM (3584 bytes)
0 F 1 0 0H 0 F 0 F FH 0 F 1 0 0H
Program/data area (3072 bytes)
FF 1 0 0H
External memory (980736 bytes)
Note 1
1 7 F F FH 1 0 0 0 0H
1 7 F F FH
Note 2
0 F 0 F FH
Note 4
0 1 0 0 0H 0 0 F F FH
Program/data area CALLF entry area (2 Kbytes)
0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH
Note 3
Internal ROM (61696 bytes)
1 8 0 0 0H 1 7 F F FH
CALLT table area (64 bytes) Vector table area (64 bytes)
Internal ROM (96 Kbytes)
Note 4
0 0 0 0 0H
0 0 0 0 0H
0 0 0 0 0H
Notes 1. Accessed in external memory expansion mode. 2. This 3840-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0H instruction: 94464 bytes, on execution of LOCATION 0FH instruction: 98304 bytes
23
4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.
24
On execution of LOCATION 0H instruction
F F F F FH
Figure 6-2. Memory Map of PD784215, 784215Y
On execution of LOCATION 0FH instruction
F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH
function registers (SFR) (256 bytes)
External memory (896 Kbytes)
Note 1
0 FEF FH
F FEF FH
General-purpose registers (128 bytes)
0 FE8 0H 0 FE 7 FH FFE8 0H F FE 7 FH FEB 0 0H FEAF FH
Internal RAM (5120 bytes)
2 0 0 0 0H 1 F F F FH 1 0 0 0 0H 0 F F F FH Special 0 F FDFH Note 1 0 F FD0H 0 FF 0 0H 0 FEF FH
PD784214,784215,784216,784214Y,784215Y,784216Y
Internal ROM (65536 bytes)
function registers (SFR) (256 bytes)
0 F E 3 BH 0 FE0 6H
Macro service control word area (54 bytes) Data area (512 bytes)
F F E 3 BH FFE0 6H
Data Sheet U11725EJ2V0DS00
Internal RAM (5120 bytes)
0 EB 0 0H 0 EAF FH
0 FD0 0H 0 FCF FH
F FD0 0H F FCF FH
Program/data area (4608 bytes)
0 EB 0 0H FEB 0 0H 1 F F F FH
External memory (912128 bytes)
Note 1
1 F F F FH 1 0 0 0 0H
Note 2
0 EAF FH
Note 4
0 1 0 0 0H 0 0 F F FH
Program/data area
Note 3
Internal ROM (60160 bytes)
0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H 0 0 0 0 0H
CALLF entry area (2 Kbytes)
2 0 0 0 0H 1 F F F FH
CALLT table area (64 bytes) Vector table area (64 bytes)
Internal ROM (128 Kbytes)
Note 4
0 0 0 0 0H
Notes 1. Accessed in external memory expansion mode. 2. This 5376-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0H instruction: 125696 bytes, on execution of LOCATION 0FH instruction: 131072 bytes 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.
Figure 6-3. Memory Map of PD784216, 784216Y
On execution of LOCATION 0H instruction
F F F F FH
On execution of LOCATION 0FH instruction
F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH
function registers (SFR) (256 bytes)
External memory (896 Kbytes)
Note 1
0 FEF FH
F FEF FH
General-purpose registers (128 bytes)
0 FE8 0H 0 FE 7 FH FFE8 0H F FE 7 FH FDF 0 0H FDE F FH
Internal RAM (8192 bytes)
PD784214,784215,784216,784214Y,784215Y,784216Y
2 0 0 0 0H 1 F F F FH 1 0 0 0 0H 0 F F F FH Special 0 F FDFH Note 1 0 F FD0H 0 FF 0 0H 0 FEF FH
Internal ROM (65536 bytes)
function registers (SFR) (256 bytes)
0 F E 3 BH 0 FE0 6H
Macro service control word area (54 bytes) Data area (512 bytes)
F F E 3 BH FFE0 6H
Data Sheet U11725EJ2V0DS00
Internal RAM (8192 bytes)
0DF 0 0H 0 DE F FH
0 FD0 0H 0 FCF FH
F FD0 0H F FCF FH
Program/data area (7680 bytes)
0DF 0 0H FDF 0 0H 1 F F F FH
External memory (909056 bytes)
Note 1
1 F F F FH 1 0 0 0 0H
Note 2
0 DE F FH
Note 4
0 1 0 0 0H 0 0 F F FH
Program/data area
Note 3
Internal ROM (57088 bytes)
0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H 0 0 0 0 0H
CALLF entry area (2 Kbytes)
2 0 0 0 0H 1 F F F FH
CALLT table area (64 bytes) Vector table area (64 bytes)
Internal ROM (128 Kbytes)
Note 4
0 0 0 0 0H
Notes 1. Accessed in external memory expansion mode. 2. This 8448-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0H instruction: 122624 bytes, on execution of LOCATION 0FH instruction: 131072 bytes
25
4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.
PD784214,784215,784216,784214Y,784215Y,784216Y
6.2 CPU Registers
6.2.1 General-purpose registers Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can be also used in pairs as a 16-bit register. Of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24-bit address specification registers. Eight banks of these register sets are available which can be selected by using software or the context switching function. The general-purpose registers except V, U, T, and W registers for address expansion are mapped to the internal RAM. Figure 6-4. General-Purpose Register Format
A (R1) AX (RP0) B (R3) BC (RP1) R5 RP2 R7 RP3 V VVP (RG4) U R11 R9 VP (RP4)
X (R0) C (R2) R4 R6 R8
R10
UP (RP5) UUP (RG5) T D (R13) E (R12) DE (RP6) TDE (RG6) H (R15) L (R14) 8 banks WHL (RG7) Parentheses ( HL (RP7) ) indicate an absolute name.
W
Caution
Registers R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of the PSW to 1. However, use this function only for recycling the program of the 78K/III Series.
26
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
6.2.2 Control registers (1) Program counter (PC) The program counter is a 20-bit register whose contents are automatically updated when the program is executed. Figure 6-5. Program Counter (PC) Format
19 PC 0
(2) Program status word (PSW) This register holds the statuses of the CPU. Its contents are automatically updated when the program is executed. Figure 6-6. Program Status Word (PSW) Format
15 PSWH PSW 7 PSWL S 6 Z 5 RSS
Note
14 RBS2
13 RBS1
12 RBS0
11 -
10 -
9 -
8 -
UF
4 AC
3 IE
2 P/V
1 0
0 CY
Note This flag is provided to maintain compatibility with the 78K/III Series. Be sure to clear this flag to 0, except when the software for the 78K/III Series is used. (3) Stack pointer (SP) This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the higher 4 bits of this pointer. Figure 6-7. Stack Pointer (SP) Format
23 SP 0 0 0 20 0 0
Data Sheet U11725EJ2V0DS00
27
PD784214,784215,784216,784214Y,784215Y,784216Y
6.2.3 Special function registers (SFRs) The special function registers, such as the mode registers and control registers of the internal peripheral hardware, are registers to which special functions are allocated. These registers are mapped to a 256-byte space of addresses 0FF00H through 0FFFFH Note. Note On execution of the LOCATION 0H instruction. FFF00H through FFFFFH on execution of the LOCATION 0FH instruction. Caution Do not access an address in this area to which no SFR is allocated. If such an address is accessed by mistake, the PD784216 may be in the deadlock status. This deadlock status can be cleared only by inputting the RESET signal. Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows: * Symbol ............................... Symbol indicating an SFR. C compiler (CC78K4). * R/W .................................... Indicates whether the SFR is read-only, write-only, or read/write. R/W: Read/write R: W: Read-only Write-only This symbol is reserved for NEC's assembler
(RA78K4). It can be used as sfr variable by the #pragma sfr command with the
* Bit units for manipulation .. Bit units in which the value of the SFR can be manipulated. SFRs that can be manipulated in 16-bit units can be described as the operand sfrp of an instruction. To specify the address of this SFR, describe an even address. SFRs that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction. * After reset .......................... Indicates the status of the register when the RESET signal has been input.
28
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
Table 6-1. Special Function Register (SFR) List (1/4)
AddressNote 1 Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 bit 0FF00H 0FF01H 0FF02H 0FF03H 0FF04H 0FF05H 0FF06H 0FF07H 0FF08H 0FF09H 0FF0AH 0FF0CH 0FF0DH 0FF10H 0FF11H 0FF12H 0FF13H 0FF14H 0FF15H 0FF16H 0FF18H 0FF1AH 0FF1CH 0FF20H 0FF22H 0FF23H 0FF24H 0FF25H 0FF26H 0FF27H 0FF28H 0FF29H 0FF2AH 0FF2CH 0FF2DH Capture/compare register 00 (16-bit timer/event counter) Capture/compare register 01 (16-bit timer/event counter) Capture/compare control register 0 16-bit timer mode control register 16-bit timer output control register Prescaler mode register 0 Port mode 0 register Port mode 2 register Port mode 3 register Port mode 4 register Port mode 5 register Port mode 6 register Port mode 7 register Port mode 8 register Port mode 9 register Port mode 10 register Port mode 12 register Port mode 13 register CRC0 TMC0 TOC0 PRM0 PM0 PM2 PM3 PM4 PM5 PM6 PM7 PM8 PM9 PM10 PM12 PM13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FFH 00H CR01 -- -- CR00 R/W -- -- Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 12 Port 13 16-bit timer counter P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P12 P13 TM0 R R/W R R/W -- 8 bits -- 16 bits -- -- -- -- -- -- -- -- -- -- -- -- -- 0000H 00HNote 2 After Reset
Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed. 2. Because each port is initialized to input mode after reset, "00H" is not actually read. The output latch is initialized to "0".
Data Sheet U11725EJ2V0DS00
29
PD784214,784215,784216,784214Y,784215Y,784216Y
Table 6-1. Special Function Register (SFR) List (2/4)
AddressNote Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 bit 0FF30H 0FF32H 0FF33H 0FF37H 0FF38H 0FF3AH 0FF3CH 0FF40H 0FF42H 0FF4EH 0FF50H 0FF51H 0FF52H 0FF53H 0FF54H 0FF55H 0FF56H 0FF57H 0FF60H 0FF61H 0FF62H 0FF63H 0FF64H 0FF65H 0FF66H 0FF67H 0FF68H 0FF69H 0FF6AH 0FF6BH 0FF6CH 0FF6DH 0FF6EH 0FF6FH 0FF70H 0FF71H 0FF72H 0FF73H Pull-up resistor option register 0 Pull-up resistor option register 2 Pull-up resistor option register 3 Pull-up resistor option register 7 Pull-up resistor option register 8 Pull-up resistor option register 10 Pull-up resistor option register 12 Clock output control register Port function control register Pull-up resistor option register 8-bit timer counter 1 8-bit timer counter 2 Compare register 10 (8-bit timer/event counter 1) Compare register 20 (8-bit timer/event counter 2) 8-bit timer mode control register 1 8-bit timer mode control register 2 Prescaler mode register 1 Prescaler mode register 2 8-bit timer counter 5 8-bit timer counter 6 8-bit timer counter 7 8-bit timer counter 8 Compare register 50 (8-bit timer/event counter 5) Compare register 60 (8-bit timer/event counter 6) Compare register 70 (8-bit timer/event counter 7) Compare register 80 (8-bit timer/event counter 8) 8-bit timer mode control register 5 8-bit timer mode control register 6 8-bit timer mode control register 7 8-bit timer mode control register 8 Prescaler mode register 5 Prescaler mode register 6 Prescaler mode register 7 Prescaler mode register 8 Asynchronous serial interface mode register 1 Asynchronous serial interface mode register 2 Asynchronous serial interface status register 1 Asynchronous serial interface status register 2 PU0 PU2 PU3 PU7 PU8 PU10 PU12 CKS PF2 PUO TM1 TM2 CR10 CR1W CR20 TMC1 TMC1W TMC2 PRM1 PRM1W PRM2 TM5 TM5W R TM6 TM7 TM7W TM8 CR50 CR5W CR60 CR70 CR7W CR80 TMC5 TMC5W TMC6 TMC7 TMC7W TMC8 PRM5 PRM5W PRM6 PRM7 PRM7W PRM8 ASIM1 ASIM2 ASIS1 ASIS2 R R/W R/W TM1W R R/W -- -- -- -- -- -- -- -- -- -- -- -- 8 bits -- -- -- -- 00H 16 bits -- -- -- -- -- -- -- -- -- -- 0000H 00H After Reset
Note When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed.
30
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
Table 6-1. Special Function Register (SFR) List (3/4)
AddressNote 1 Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 bit 0FF74H Transmit shift register 1 Receive buffer register 1 0FF75H Transmit shift register 2 Receive buffer register 2 0FF76H 0FF77H 0FF7AH 0FF80H 0FF81H 0FF83H 0FF84H 0FF85H 0FF86H 0FF87H 0FF8CH 0FF90H 0FF91H 0FF92H 0FF94H 0FF95H 0FF96H 0FF98H 0FF99H 0FF9AH 0FF9BH 0FF9CH 0FFA0H 0FFA2H 0FFA8H 0FFA9H 0FFAAH 0FFACH 0FFADH 0FFAEH 0FFAFH 0FFB0H 0FFB2H 0FFB4H Baud rate generator control register 1 Baud rate generator control register 2 Oscillation mode select register A/D converter mode register A/D converter input select register A/D conversion result register D/A conversion value setting register 0 D/A conversion value setting register 1 D/A converter mode register 0 D/A converter mode register 1 External bus type select register Serial operation mode register 0 Serial operation mode register 1 Serial operation mode register 2 Serial I/O shift register 0 Serial I/O shift register 1 Serial I/O shift register 2 Real-time output buffer register L Real-time output buffer register H Real-time output port mode register Real-time output port control register Watch timer mode control register External interrupt rising edge enable register External interrupt falling edge enable register In-service priority register Interrupt select control register Interrupt mode control register Interrupt mask flag register 0L Interrupt mask flag register 0H Interrupt mask flag register 1L Interrupt mask flag register 1H I 2C bus control registerNote 2 TXS1 RXB1 TXS2 RXB2 BRGC1 BRGC2 CC ADM ADIS ADCR DACS0 DACS1 DAM0 DAM1 EBTS CSIM0 CSIM1 CSIM2 SIO0 SIO1 SIO2 RTBL RTBH RTPM RTPC WTM EGP0 EGN0 ISPR SNMI IMC MK0L MK0 MK0H MK1L MK1 MK1H IICC0 SRPM0 SVA0 R R/W R R/W W R W R R/W -- -- -- -- -- -- -- -- -- -- 8 bits -- -- -- 00H 16 bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 80H FFFFH Undefined 00H 00H FFH After Reset
Prescaler mode register for serial clock Slave address register
Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed. 2. PD784216Y Subseries only.
Data Sheet U11725EJ2V0DS00
31
PD784214,784215,784216,784214Y,784215Y,784216Y
Table 6-1. Special Function Register (SFR) List (4/4)
AddressNote 1 Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 bit 0FFB6H 0FFB8H 0FFC0H 0FFC2H 0FFC4H 0FFC7H 0FFCEH 0FFCFH 0FFD0H to 0FFDFH 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H 0FFE6H 0FFE7H 0FFE8H 0FFE9H 0FFEAH 0FFEBH 0FFECH 0FFEDH 0FFEEH 0FFEFH 0FFF0H 0FFF1H 0FFF2H 0FFF3H 0FFF4H 0FFF5H 0FFF6H 0FFF7H 0FFF8H 0FFF9H 0FFFAH Interrupt control register (INTWDTM) Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3) Interrupt control register (INTP4) Interrupt control register (INTP5) Interrupt control register (INTP6) Interrupt control register (INTCSI0) Interrupt control register (INTIIC0/INTSER1) Interrupt control register (INTSR1/INTCSI1) Interrupt control register (INTST1) Interrupt control register (INTSER2) Interrupt control register (INTSR2/INTCSI2) Interrupt control register (INTST2) Interrupt control register (INTTM3) Interrupt control register (INTTM00) Interrupt control register (INTTM01) Interrupt control register (INTTM1) Interrupt control register (INTTM2) Interrupt control register (INTAD) Interrupt control register (INTTM5) Interrupt control register (INTTM6) Interrupt control register (INTTM7) Interrupt control register (INTTM8) Interrupt control register (INTWT) Interrupt control register (INTKR) WDTIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 CSIIC0 SERIC1 SRIC1 STIC1 SERIC2 SRIC2 STIC2 TMIC3 TMIC00 TMIC01 TMIC1 TMIC2 ADIC TMIC5 TMIC6 TMIC7 TMIC8 WTIC KRIC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 43H I 2C bus status registerNote 2 IICS0 IIC0 STBC WDM MM PWC1 PCS OSTS -- R R/W R R/W -- -- 8 bits 16 bits -- -- -- -- -- -- -- -- -- 30H 00H 20H AAH 32H 00H -- 00H After Reset
Serial shift regiter Standby control register Watchdog timer mode register Memory expansion mode register Programmable wait control register 1 Clock status register Oscillation stabilization time specification register External SFR area
Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed. 2. PD784216Y Subseries only.
32
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
7. PERIPHERAL HARDWARE FUNCTIONS 7.1 Ports
The ports shown in Figure 7-1 are provided to make various control operations possible. Table 7-1 shows the function of each port. Ports 0, 2 through 8, 10 and 12 can be connected to internal pull-up resistors by software when inputting. Figure 7-1. Port Configuration
PORT 7

P70 P72 P80
P00
PORT 8
P06
PORT 0
P87 P90
P10 to P17
8
PORT 1
PORT 9
P20 P95 P100 P103 P120
PORT 10
PORT 12
P27 P30
PORT 2 PORT 3 PORT 4 PORT 5 PORT 6
PORT 13
P127 P130 P131
P37 P40
P47 P50
P57 P60
P67
Data Sheet U11725EJ2V0DS00
33
PD784214,784215,784216,784214Y,784215Y,784216Y
Table 7-1. Port Functions
Port Name Pin Name Function Specification of Pull-up Resistor Connection by Software Can be specified in 1-bit units -- Can be specified in 1-bit units Can be specified in 1-bit units Can be specified in 1-port units
Port 0 Port 1 Port 2 Port 3 Port 4
P00 to P06 P10 to P17 P20 to P27 P30 to P37 P40 to P47
* Can be set in input or output mode in 1-bit units * Input port * Can be set in input or output mode in 1-bit units * Can be set in input or output mode in 1-bit units * Can be set in input or output mode in 1-bit units * Can directly drive LEDs * Can be set in input or output mode in 1-bit units * Can directly drive LEDs * Can be set in input or output mode in 1-bit units * Can be set in input or output mode in 1-bit units * Can be set in input or output mode in 1-bit units * N-ch open-drain I/O port * Can be set in input or output mode in 1-bit units * Can directly drive LEDs * Can be set in input or output mode in 1-bit units * Can be set in input or output mode in 1-bit units * Can be set in input or output mode in 1-bit units
Port 5
P50 to P57
Can be specified in 1-port units
Port 6 Port 7 Port 8 Port 9
P60 to P67 P70 to P72 P80 to P87 P90 to P95
Can be specified in 1-port units Can be specified in 1-bit units Can be specified in 1-bit units --
Port 10 Port 12 Port 13
P100 to P103 P120 to P127 P130, P131
Can be specified in 1-bit units Can be specified in 1-bit units --
7.2 Clock Generation Circuit
An on-chip clock generation circuit necessary for operation is provided. This clock generation circuit has a frequency divider. If high-speed operation is not necessary, the internal operating frequency can be lowered by the frequency divider to reduce the current consumption. Figure 7-2. Block Diagram of Clock Generation Circuit
XT1 XT2
Subsystem clock oscillator
fXT
Watch timer, clock output function Prescaler
X2
Main system clock oscillator
IDLE control circuit
Selector
X1
fX
Frequency divider fX
fXX
Prescaler
Clock to peripheral hardware
2 Bit 2 of standby control register (STBC) (MCK) = 1 when the subclock is selected for STOP and CPU
fXX fXX fXX 2 22 23 STOP, IDLE control circuit
Selector
HALT control circuit
CPU clock (fCPU) Internal system clock (fCLK)
34
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
Figure 7-3. Example of Using Main System Clock Oscillator
(1) Crystal/ceramic oscillation
(2) External clock
X2
X2
X1 VSS Crystal resonator or ceramic resonator
External clock PD74HCU04
X1
Figure 7-4. Example of Using Subsystem Clock Oscillator
(1) Crystal oscillation
(2) External clock
32.768 kHz
VSS XT2 External clock
XT2
XT1
XT1
PD74HCU04
Caution
When using the main system clock and subsystem clock oscillator, wire the broken-lines portions in Figures 7-3 and 7-4 as follows to avoid adverse influence from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always keep the ground point of the oscillator capacitor to the same potential as VSS. Do not ground the capacitor to a ground pattern in which a high current flows. * Do not fetch signals from the oscillator. Note that the subsystem clock oscillator has a low amplification factor to reduce the current consumption.
Data Sheet U11725EJ2V0DS00
35
PD784214,784215,784216,784214Y,784215Y,784216Y
7.3 Real-Time Output Port
The real-time output function is to transfer data set in advance to the real-time output buffer register to the output latch as soon as the timer interrupt or external interrupt has occurred in order to output the data to an external device. The pins that output the data to the external device constitute a port called a real-time output port. Because the real-time output port can output signals without jitter, it is ideal for controlling a stepping motor. Figure 7-5. Block Diagram of Real-Time Output Port
Internal bus Real-time output port control register (RTPC) RTPOE BYTE EXTR
INTP2TRG INTTM1 INTTM2 Output trigger control circuit
High-order 4 bits of real-time output buffer register (RTBH)
Low-order 4 bits of real-time output buffer register (RTBL) Real-time output port mode register (RTPM)
Port 12 output latch
Real-time output port output latch
P127************************************** P120
RTP7************************************** RTP0
RTPOE bit
P12n/RTPn pin output (n = 0 to 7)
P127/************************************** P120/ RTP7 RTP0
36
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
7.4 Timer/Event Counter
One unit of 16-bit timers/event counters and six units of 8-bit timers/event counters are provided. Because a total of eight interrupt requests are supported, these timers/counters can be used as eight units of timers/event counters. Table 7-2. Operations of Timers/Counters
Name Item Count width 8 bits 16 bits Operation mode Function Interval timer External event counter Timer output PPG output PWM output Square wave output One-shot pulse output Pulse width measurement Number of interrupt requests 16-Bit 8-Bit 8-Bit 8-Bit 8-Bit 8-Bit 8-Bit Timer/event Timer/event Timer/event Timer/event Timer/event Timer/event Timer/event Counter Counter 1 Counter 2 Counter 5 Counter 6 Counter 7 Counter 8 -- 1ch 1ch -- 2 inputs 2 1ch 1ch -- -- -- 1 1ch 1ch -- -- -- 1 1ch 1ch -- -- -- 1 1ch 1ch -- -- -- 1 1ch 1ch -- -- -- 1 1ch 1ch -- -- -- 1
Data Sheet U11725EJ2V0DS00
37
PD784214,784215,784216,784214Y,784215Y,784216Y
Figure 7-6. Block Diagram of Timers/Event Counters 16-bit timer/event counter
fXX/4 fXX/16 INTTM3
Selector
Clear
16-bit timer counter (TM0)
16
Selector
TI01
16 INTTM01 TI00 Edge detection circuit 16-bit capture/compare register 01 (CR01)
Output control circuit
Edge detection circuit
INTTM00 16-bit capture/compare register 00 (CR00)
TO0
8-bit timer/event counter 1, 5, 7
fXX/22 fXX/23 Clear
Selector
fXX/2
4
fXX/25 fXX/2
7
8-bit timer counter n (TMn) 8
OVF Output control circuit TOn
fXX/29 TIn Edge detection circuit
8-bit compare register n0 (CRn0) INTTMn + 1
Selector
INTTMn
Remarks 1. n = 1, 5, 7 2. OVF: overflow flag 8-bit timer/event counter 2, 6, 8
TMn-1 fXX/22 fXX/23 fXX/24 fXX/25 fXX/2
7
Clear
Selector
8-bit timer counter n (TMn) 8
OVF Output control circuit TOn
fXX/29 TIn Edge detection circuit 8-bit compare register n0 (CRn0) INTTMn
Remarks 1. n = 2, 6, 8 2. OVF: overflow flag
38
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
7.5 A/D Converter
An A/D converter converts an analog input variable into a digital signal. This microcontroller is provided with an A/D converter with a resolution of 8 bits and 8 channels (ANI0 through ANI7). This A/D converter is of successive approximation type and the result of conversion is stored to an 8-bit A/D conversion result register (ADCR). The A/D converter can be started in the following two ways: * Hardware start Conversion is started by trigger input (P03). * Software start Conversion is started by setting the A/D converter mode register (ADM). One analog input channel is selected from ANI0 through ANI7 for A/D conversion. When A/D conversion is started by means of hardware start, conversion is stopped after it has been completed. When conversion is started by means of software start, A/D conversion is repeatedly executed, and each time conversion has been completed, an interrupt request (INTAD) is generated. Figure 7-7. Block Diagram of A/D Converter
Series resistor string ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 AVSS Successive approximation register (SAR) Sample & hold circuit AVDD AVREF0
INTP3/P03
Edge detection circuit
Selector
Voltage comparator
Control circuit
Tap selector
INTAD
Edge detection circuit
A/D conversion result register (ADCR) INTP3 Internal bus
Data Sheet U11725EJ2V0DS00
39
PD784214,784215,784216,784214Y,784215Y,784216Y
7.6 D/A Converter
A D/A converter converts an input digital signal into an analog voltage. This microcontroller is provided with a voltage output type D/A converter with a resolution of 8 bits and two channels. The conversion method is of R-2R resistor ladder type. D/A conversion is started by setting DACE0 of the D/A converter mode register 0 (DAM0) and DACE1 of the D/ A converter mode register 1 (DAM1). The D/A converter operates in the following two modes: * Normal mode The converter outputs an analog voltage immediately after it has completed D/A conversion. * Real-time output mode The converter outputs an analog voltage in synchronization with an output trigger after it has completed D/A conversion. Figure 7-8. Block Diagram of D/A Converter
DACS0 8 2R ANO0 AVREF1 2R R
Selector R 2R DACS1 2R 8 2R ANO1 2R R
Selector R 2R AVSS
2R
40
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
7.7 Serial Interface
Three independent serial interface channels are provided. * Asynchronous serial interface (UART)/3-wire serial I/O (IOE) x 2 * Clocked serial interface (CSI) x 1 * 3-wire serial I/O (IOE) * I2C bus interface (PD784216Y Subseries only) Therefore, communication with an external system and local communication within the system can be simultaneously executed (refer to Figure 7-9). Figure 7-9. Example of Serial Interface (a) UART + I2C
PD784216Y (master) PD4711A
[UART] RS-232-C driver/receiver RxD1 TxD1
Port
VDD [I2C]
VDD
PD780078Y (slave)
SDA SCL
SDA0 SCL0
PD780308Y (slave)
SDA LCD
PD4711A
[UART] RxD2 RS-232-C driver/receiver TxD2
Port
SCL
(b) UART + 3-wire serial I/O
PD784216 (master)
PD4711A
[UART] RxD2 RS-232-C driver/receiver TxD2

PD753106 (slave)
[3-wire serial I/O] SI SO SCK Note Port INT
SO1 SI1 SCK1 INTPm Port
Port
Note Handshake line
Data Sheet U11725EJ2V0DS00
41
PD784214,784215,784216,784214Y,784215Y,784216Y
7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) Two channels of serial interfaces that can select an asynchronous serial interface mode and 3-wire serial I/O mode are provided. (1) Asynchronous serial interface mode In this mode, data of 1 byte following the start bit is transmitted or received. Because an on-chip baud rate generator is provided, a wide range of baud rates can be set. Moreover, the clock input to the ASCK pin can be divided to define a baud rate. When the baud rate generator is used, a baud rate conforming to the MIDI standard (31.25 kbps) can be also obtained. Figure 7-10. Block Diagram in Asynchronous Serial Interface Mode
Internal bus 8 Receive buffer register 1, 2 (RXB1, RXB2) 8 RxD1, RxD2 TxD1, TxD2 Receive control parity check INTSR1, INTSR2 Transmit control parity append INTST1, INTST2 Receive shift register 1, 2 (RX1, RX2) Transmit shift register 1, 2 (TXS1, TXS2) 8
Baud rate generator
5-bit counter x 2 Transmit/receive clock generation ASCK1, ASCK2
Selector
fXX-fXX/25
42
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
(2) 3-wire serial I/O mode In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in synchronization with this clock. This mode is used to communicate with a device having the conventional clocked serial interface. Basically, communication is established by using three lines: serial clocks (SCK1 and SCK2), serial data inputs (SI1 and SI2), and serial data outputs (SO1 and SO2). To connect two or more devices, a handshake line is necessary. Figure 7-11. Block Diagram in 3-wire Serial I/O Mode
Internal bus
8
SI1, SI2
Serial I/O shift register 1, 2 (SIO1, SIO2)
SO1, SO2 SCK1, SCK2 Serial clock counter Serial clock control circuit Interrupt generation circuit INTCSI1, INTCSI2 TO2 fXX/8 fXX/16
Selector
Data Sheet U11725EJ2V0DS00
43
PD784214,784215,784216,784214Y,784215Y,784216Y
7.7.2 Clocked serial interface (CSI) In this mode, the master device starts transfer by making the serial clock active and communicates 1-byte data in synchronization with this clock. (1) 3-wire serial I/O mode This mode is to communicate with devices having the conventional clocked serial interface. Basically, communication is established in this mode with three lines: one serial clock (SCK0) and two serial data (SI0 and SO0) lines. Generally, a handshake line is necessary to check the reception status. Figure 7-12. Block Diagram in 3-wire Serial I/O Mode
Internal bus
8
SI0
Serial I/O shift register 0 (SIO0)
SO0 SCK0 Serial clock counter Serial clock control circuit Interrupt generation circuit INTCSI0
Selector
TO2 fXX/8 fXX/16
(2) I2C bus (Inter IC) bus mode (supporting multi-master) (PD784216Y Subseries only) This mode is for communication with devices conforming to the I2C bus format. This mode is for transferring 8-bit data between two or more devices by using two lines: a seiral clock (SCL0) and a serial data bus (SDA0). During transfer, a "start condition", "data", and "stop condition" can be output onto the serial data bus. During reception, these data are automatically detected by hardware.
44
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
Figure 7-13. Block Diagram of I2C Bus Mode
Internal bus 8 Direction control circuit 8 SDA0 Serial I/O shift register 0 (SIO0) Output latch 8 Slave address register (SVA0) Wake-up control circuit
Acknowledge generation circuit Start condition/acknowledge detection circuit Stop condition detection circuit SCL0 Serial clock counter Serial clock control circuit
Interrupt generation circuit
INTIIC0
Selector
TO2/18 to TO2/68 fxx/24 to fxx/178
7.8 Clock Output Function
Clocks of the following frequencies can be output as clock output. * 97.7 kHz/195 kHz/391 kHz/781 kHz/1.56 MHz/3.13 MHz/6.25 MHz/12.5 MHz (@ 12.5-MHz operation with main system clock) * 32.768 kHz (@ 32.768-kHz operation with subsystem clock) Figure 7-14. Block Diagram of Clock Output Function
fXX fXX/2 fXX/22 fXX/24 fXX/25 fXX/2
6
Selector
fXX/23
Synchronization circuit
Output control circuit
PCL
fXX/27 fXT
Data Sheet U11725EJ2V0DS00
45
PD784214,784215,784216,784214Y,784215Y,784216Y
7.9 Buzzer Output Function
Clocks of the following frequencies can be output as buzzer output. * 1.5 kHz/3.1 kHz/6.1 kHz/12.2 kHz (@ 12.5-MHz operation with main system clock) Figure 7-15. Block Diagram of Buzzer Output Function
fXX/210 fXX/211 fXX/2
12
Selector
Output control circuit
BUZ
fXX/213
7.10 Edge Detection Function
The interrupt input pins (INTP0, INTP1, NMI/INTP2, INTP3 through INTP6) are used not only to input interrupt requests but also to input trigger signals to the internal hardware units. Because these pins operate at an edge of the input signal, they have a function to detect an edge. Moreover, a noise reduction function is also provided to prevent erroneous detection due to noise.
Pin Name NMI INTP0 through INTP6 Detectable Edge Either or both of rising and falling edges Noise Reduction By analog delay
7.11 Watch Timer
The watch timer has the following functions: * Watch timer * Interval timer The watch timer and interval timer functions can be used at the same time. (1) Watch timer The watch timer sets the WTIF flag of the interrupt control register (WTIC) at time intervals of 0.5 seconds by using the 32.768-kHz subsystem clock. (2) Interval timer The interval timer generates an interrupt request (INTTM3) at predetermined time intervals.
46
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
Figure 7-16. Block Diagram of Watch Timer
fW
Prescaler fW 24 fW 25 fW 26 fW 27 fW 28 fW 29
Selector
fXX/2
Selector
7
Selector
5-bit counter
fW 214 INTWT
fXT
fW 25
Selector
INTTM3 To 16-bit timer/counter
7.12 Watchdog Timer
A watchdog timer is provided to detect a CPU runaway. This watchdog timer generates a non-maskable or maskable interrupt unless it is cleared by software within a specified interval time. Once enabled to operate, the watchdog timer cannot be stopped by software. Whether the interrupt by the watchdog timer or the interrupt input from the NMI pin takes precedence can be specified. Figure 7-17. Block Diagram of Watchdog Timer
fCLK
Timer
fCLK/221 fCLK/220
Selector
fCLK/219 fCLK/217
INTWDT
Clear signal
Remark fCLK: Internal system clock (fXX to fXX/8)
Data Sheet U11725EJ2V0DS00
47
PD784214,784215,784216,784214Y,784215Y,784216Y
8. INTERRUPT FUNCTION
As the servicing in response to an interrupt request, the three types shown in Table 8-1 can be selected by program. Table 8-1. Servicing of Interrupt Request
Servicing Mode Vectored interrupt Entity of Servicing Software Servicing Branches and executes servicing routine (servicing is arbitrary) Automatically switches register bank, branches and executes servicing routine (servicing is arbitrary) Firmware Executes data transfer between memory and I/O (servicing is fixed) Contents of PC and PSW Saves to and restores from stack Saves to or restores from fixed area in register bank
Context switching
Macro service
Retained
8.1 Interrupt Sources
Table 8-2 shows the interrupt sources available. As shown, interrupts are generated by 29 types of sources, execution of the BRK instruction, BRKCS instruction, or an operand error. The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt servicing and that which of the two or more interrupts that simultaneously occur should be serviced first. When the macro service function is used, however, nesting always proceeds. The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having the same priority, simultaneously generate (refer to Table 8-2). Table 8-2. Interrupt Sources (1/2)
Type Default Priority Software -- Name BRK instruction BRKCS instruction Operand error Source Trigger Instruction execution Instruction execution If result of exclusive OR between operands byte and byte is not FFH when MOV STBC, #byte instruction, MOV WDM, #byte instruction, or LOCATION instruction is executed Pin input edge detection Overflow of watchdog timer Overflow of watchdog timer Pin input edge detection External Internal Internal External -- Internal/ External -- Macro Service --
Non-maskable
--
NMI INTWDT
Maskable
0 (highest) 1 2 3 4 5 6 7 8
INTWDTM INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTIIC0 INTCSI0
End of I2C bus transfer by CSI0 End of 3-wire transfer by CSI0 Occurrence of UART reception error in ASI1
Internal
9
INTSER1
48
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
Table 8-2. Interrupt Sources (2/2)
Type Default Priority Maskable 10 Name INTSR1 INTCSI1 11 12 13 INTST1 INTSER2 INTSR2 INTCSI2 14 15 16 INTST2 INTTM3 INTTM00 Source Trigger End of UART reception by ASI1 End of 3-wire transfer by CSI1 End of UART transmission by ASI1 Occurrence of UART reception error in ASI2 End of UART reception by ASI2 End of 3-wire transfer by CSI2 End of UART transmission by ASI2 Reference time interval signal from watch timer Signal indicating coincidence between 16-bit timer register and capture/compare register (CR00) Signal indicating coincidence between 16-bit timer register and capture/compare register (CR01) Occurrence of coincidence signal of 8-bit timer/counter 1 Occurrence of coincidence signal of 8-bit timer/counter 2 End of conversion by A/D converter Occurrence of coincidence signal of 8-bit timer/counter 5 Occurrence of coincidence signal of 8-bit timer/counter 6 Occurrence of coincidence signal of 8-bit timer/counter 7 Occurrence of coincidence signal of 8-bit timer/counter 8 Overflow of watch timer Detection of falling edge of port 8 External Internal/ External Internal Macro Service
17
INTTM01
18 19 20 21 22 23 24 25 26 (lowest)
INTTM1 INTTM2 INTAD INTTM5 INTTM6 INTTM7 INTTM8 INTWT INTKR
Remarks 1. ASI: Asynchronous Serial Interface CSI: Clocked Serial Interface 2. There are two interrupt sources for the watchdog timer: non-maskable interrupts (INTWDT) and maskable interrupts (INTWDTM). Either one should be selected for actual use.
Data Sheet U11725EJ2V0DS00
49
PD784214,784215,784216,784214Y,784215Y,784216Y
8.2 Vectored Interrupt
Execution branches to a servicing routine by using the memory contents of a vector table address corresponding to the interrupt source as the address of the branch destination. So that the CPU performs interrupt servicing, the following operations are performed: * On branching: Saves the status of the CPU (contents of PC and PSW) to stack * On returning: Restores the status of the CPU (contents of PC and PSW) from stack
To return to the main routine from an interrupt service routine, the RETI instruction is used. The branch destination address is in a range of 0 to FFFFH. Table 8-3. Vector Table Address
Interrupt Source BRK instruction TRAP0 (operand error) NMI INTWDT (non-maskable) INTWDTM (maskable) INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTIIC0 INTCSI0 INTSER0 INTSR1 INTCSI1 0018H 001AH Vector Table Address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H Interrupt Source INTST1 INTSER2 INSR2 INTCSI2 INTST2 INTTM3 INTTM00 INTTM01 INTTM1 INTTM2 INTAD INTTM5 INTTM6 INTTM7 INTTM8 INTWT INTKR 0022H 0024H 0026H 0028H 002AH 002CH 002EH 0030H 0032H 0034H 0036H 0038H 003AH Vector Table Address 001CH 001EH 0020H
50
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
8.3 Context Switching
When an interrupt request is generated or when the BRKCS instruction is executed, a predetermined register bank is selected by hardware. Context switching is a function that branches execution to a vector address stored in advance in the register bank, and to stack the current contents of the program counter (PC) and program status word (PSW) to the register bank. The branch address is in a range of 0 to FFFFH. Figure 8-1. Context Switching Operation When Interrupt Request Is Generated
0000B <7> Transfer Register bank n (n = 0 to 7) PC19-16 PC15-0 A B <2> Save (bits 8 through 11 of temporary register) <6> Exchange R5 R7 <5> Save V U Temporary register <1> Save T W D H VP UP E L X C R4 R6
Register bank (0 to 7)
<3> Switching of register bank (RBS0 to RBS2 n) <4> RSS 0 IE 0
PSW
8.4 Macro Service
This function is to transfer data between memory and a special function register (SFR) without intervention by the CPU. A macro service controller accesses the memory and SFR in the same transfer cycle and directly transfers data without loading it. Because this function does not save or restore the status of the CPU, or load data, data can be transferred at high speeds. Figure 8-2. Macro Service
Read CPU Memory Write Macro service controller
Write SFR Read
Internal bus
Data Sheet U11725EJ2V0DS00
51
PD784214,784215,784216,784214Y,784215Y,784216Y
8.5 Application Example of Macro Service
(1) Transmission of serial interface
Transmit data storage buffer (memory) Data n Data n-1
Data 2 Data 1
Internal bus
TxD1, TxD2
Transmit shift register TXS1, TXS2(SFR)
Transmit control
INTST1, INTST2
Each time macro service requests INTST1 and INTST2 are generated, the next transmit data is transferred from memory to TXS1 and TXS2. When data n (last byte) has been transferred to TXS1 and TXS2 (when the transmit data storage buffer has become empty), vectored interrupt requests INTST1 and INTST2 are generated. (2) Reception of serial interface
Receive data storage buffer (memory) Data n Data n-1
Data 2 Data 1
Internal bus
Receive buffer register RXB1, RXB2(SFR)
RxD1, RxD2
Receive shift register
Reception control
INTSR1, INTSR2
Each time macro service requests INTSR1 and INTSR2 are generated, the receive data is transferred from RXB1 and RXB2 to memory. When data n (last byte) has been transferred to memory (when the receive data storage buffer has become full), vectored interrupt requests INTSR1 and INTSR2 are generated.
52
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
9. LOCAL BUS INTERFACE
The local bus interface can connect an external memory or I/O (memory mapped I/O) and support a memory space of 1 Mbyte (refer to Figure 9-1). Figure 9-1. Example of Local Bus Interface (a) Multiplexed bus mode
PD784216
VDD SRAM CS Data bus OE WE I/O1 to I/O8 Address bus A0 to A19 Address latch
RD WR A8 to A19
ASTB
LE Q0 to Q7 D0 to D7 OE
AD0 to AD7
(b) Separate bus mode
VDD
PD784216
SRAM
CS
RD WR Address bus A0 to A19
OE WE I/O1 to I/O8 A0 to A19
Data bus
AD0 to AD7
Data Sheet U11725EJ2V0DS00
53
PD784214,784215,784216,784214Y,784215Y,784216Y
9.1 Memory Expansion
External program memory and data memory can be connected in two stages: 256 Kbytes and 1 Mbytes. To connect the external memory, ports 4 through 6 and port 8 are used. The external memory can be connected in the following two modes: * Multiplexed bus mode: The external memory is connected by using a time-division address/data bus. The number of ports used when the external memory is connected can be reduced in this mode. * Separate bus mode: The external memory is connected by using an address bus and data bus independent of each other. Because an external latch circuit is not necessary, this mode is useful for reducing the number of components and mounting area on the printed wiring board.
9.2 Programmable Wait
Wait state(s) can be inserted to the memory space (00000H through FFFFFH) while the RD and WR signals are active. In addition, there is an address wait function that extends the active period of the ASTB signal to gain the address decode time.
54
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
10. STANDBY FUNCTION
This function is to reduce the power consumption of the chip, and can be used in the following modes: * HALT mode: Stops supply of the operating clock to the CPU. This mode is used in combination with the normal operation mode for intermittent operation to reduce the average power consumption. * IDLE mode: Stops the entire system with the oscillator continuing operation. The power consumption in this mode is close to that in the STOP mode. However, the time required to restore the normal program operation from this mode is almost the same as that from the HALT mode. * STOP mode: Stops the main system clock and thereby to stop all the internal operations of the chip. Consequently, the power consumption is minimized with only leakage current flowing. * Low-power consumption mode: The main system clock is stopped with the subsystem clock used as the system clock. The CPU can operate on the subsystem clock to reduce the current consumption. * Low-power consumption HALT mode: This is a standby function in the low-power consumption mode and stops the operation clock of the CPU, to reduce the power consumption of the entire system. * Low-power consumption IDLE mode: This is a standby function in the low-power consumption mode and stops the entire system except the oscillator, to reduce the power consumption of the entire system. These modes are programmable. The macro service can be started from the HALT mode or low-power consumption HALT mode. After macro service processing is executed, the system returnes to the HALT mode again. The transition of the standby status is shown in Figure 10-1.
Data Sheet U11725EJ2V0DS00
55
PD784214,784215,784216,784214Y,784215Y,784216Y
Figure 10-1. Standby Function State Transitions
Macro service
On e Ma time cro pro se ces rvi ce sing req en ue ds st
t es qu re nds ice ing e ds rv se cess e en ro ro c ac e p ervi M im s e t ro On ac M
Low con -pow sum er ptio Retu nm rn to norm ode se al o t pera tion
LowLow-power consumption HALT mode set Low-power power consumption consumption mode (Subsystem HALT mode Interrupt requestNote 1 clock operation) (Standby) Interrupt request for masked interrupt
Low-power consumption NMI, INTP0 to INTP6 input, INTWT, key return interruptNote 2 IDLE mode (Standby) Interrupt request for masked interrupt
Low-power consumption IDLE mode set
NT
W
T,
N ke MI, y r IN etu TP ID rn 0 to LE int IN se er T ru P6 t pt N i ot np e2 u
O ST
P
se
t
me ends
M
NM RE key I, IN SE T in ret TP0 urn to put inte INT rru P6 pt Not inp u e
2
Stable os
STOP (Standby)
Interrupt request for masked interrupt
IDLE (Standby)
Interrupt request for masked interrupt
cillation ti
Interrupt request for masked interrupt
inp ut
HALT (Standby)
t, I
NT
RE
SE
T
WT
,
Wait for stable oscillation
Notes 1. Only unmasked interrupt requests 2. Only unmasked INTP0 to INTP6, INTWT, key return interrupt (P80 to P87) Remark NMI is valid only for an external input. The watchdog timer cannot be used for the release of standby (HALT mode/STOP mode/IDLE mode).
56
Data Sheet U11725EJ2V0DS00
On
e
ac ro tim se rv e pr ice oc r es equ sin es t g en ds
t, I
R ES ET in pu t
RE SE np Ti ut
RE
T SE
inp
ut
Normal operation (Main system clock operation)
Macro service request One time processing ends Macro service ends
Macro service
Int t es qu t re pt inpu ru T t er SE T se L HA RE
PD784214,784215,784216,784214Y,784215Y,784216Y
11. RESET FUNCTION
When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized (reset). During the reset period, oscillation of the main system clock is unconditionally stopped. Consequently, the current consumption of the entire system can be reduced. When the RESET signal goes high, the reset status is cleared, oscillation stabilization time (84.0 ms at 12.5-MHz operation) elapses, the contents of the reset vector table are set to the program counter (PC), execution branches to an address set to the PC, and program execution is started from that branch address. Therefore, the program can be reset and started from any address. Figure 11-1. Oscillation of Main System Clock during Reset Period
Main system clock oscillator Oscillation is unconditionally stopped during reset period fCLK
RESET input Oscillation stabilization time
The RESET input pin has an analog delay noise elimination circuit to prevent malfunctioning due to noise. Figure 11-2. Acknowledgement of Reset Signal
Analog delay
Analog delay
Oscillation Analog stabilization delay time
RESET input
Internal reset signal
Internal clock
Data Sheet U11725EJ2V0DS00
57
PD784214,784215,784216,784214Y,784215Y,784216Y
12. INSTRUCTION SET
(1) 8-bit instructions (The instructions in parentheses are combinations realized by describing A as r) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC Table 12-1. Instruction List by 8-Bit Addressing
Second Operand #byte A r r' First Operand A (MOV) ADD
Note 1
saddr saddr'
sfr
!addr16 !!addr24
mem [saddrp] [%saddrg]
r3 PSWL PSWH MOV
[WHL+] [WHL-]
n
None Note 2
(MOV) (XCH)
MOV XCH
(MOV) Note 6 (XCH) Note 6
MOV (XCH)
(MOV) (XCH)
MOV XCH
(MOV) (XCH) (ADD) Note 1 ROR Note 3 MULU DIVUW INC DEC
(ADD) Note 1 (ADD) Note 1 (ADD) Notes 1,6 (ADD) Note 1 ADD Note 1 ADD Note 1 r MOV ADD
Note 1
(MOV) (XCH)
MOV XCH
MOV XCH
MOV XCH
MOV XCH
(ADD) Note 1 ADD Note 1 ADD Note 1 ADD Note 1
saddr
MOV ADD
Note 1
(MOV) Note 6
MOV
MOV XCH ADD Note 1
INC DEC DBNZ PUSH POP
(ADD) Note 1 ADD Note 1
sfr
MOV
MOV
MOV
ADD Note 1 (ADD) Note 1 ADD Note 1 !addr16 !!addr24 mem [saddrp] [%saddrg] mem3 MOV (MOV) ADD Note 1 MOV ADD Note 1 MOV
ROR4 ROL4
r3 PSWL PSWH B, C STBC, WDM [TDE+] [TDE-]
MOV
MOV
DBNZ MOV (MOV) (ADD)
Note 1
MOVBK Note 5
MOVM Note 4
Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as that of ADD. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as that of ROR. 4. The operands of XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as that of MOVM. 5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as that of MOVBK. 6. The code length of some instructions having saddr2 as saddr in this combination is short.
58
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
(2) 16-bit instructions (The instructions in parentheses are combinations realized by describing AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 12-2. Instruction List by 16-Bit Addressing
Second Operand #word AX rp rp' First Operand AX (MOVW) ADDW
Note 1
saddrp saddrp'
sfrp
!addr16 !!addr24
mem [saddrp] [%saddrg]
[WHL+]
byte
n
None Note 2
(MOVW) (XCHW)
(MOVW) (MOVW) (XCHW) (XCHW)
Note 3 Note 3
MOVW (XCHW)
(MOVW) XCHW
MOVW XCHW
(MOVW) (XCHW)
(ADD) Note 1 (ADDW) Note 1 (ADDW) Note 1,3 (ADDW) Note 1 rp MOVW ADDW
Note 1
(MOVW) (XCHW) (ADDW)
Note 1
MOVW XCHW ADDW
Note 1
MOVW XCHW ADDW
Note 1
MOVW XCHW ADDW
Note 1
MOVW
SHRW SHLW
MULW Note 4 INCW DECW INCW DECW
saddrp
MOVW ADDW
Note 1
(MOVW) Note 3 (ADDW)
Note 1
MOVW ADDW
Note 1
MOVW XCHW ADDW Note 1
sfrp
MOVW
MOVW
MOVW
PUSH POP MOVTBLW
ADDW Note 1 (ADDW) Note 1 ADDW Note 1 !addr16 !!addr24 mem [saddrp] [%saddrg] PSW MOVW MOVW (MOVW) MOVW
PUSH POP
SP
ADDWG SUBWG
post
PUSH POP PUSHU POPU
[TDE+] byte
(MOVW)
SACW MACW MACSW
Notes 1. The operands of SUBW and CMPW are the same as that of ADDW. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The code length of some instructions having saddrp2 as saddrp in this combination is short. 4. The operands of MULUW and DIVUX are the same as that of MULW.
Data Sheet U11725EJ2V0DS00
59
PD784214,784215,784216,784214Y,784215Y,784216Y
(3) 24-bit instructions (The instructions in parentheses are combinations realized by describing WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 12-3. Instruction List by 24-Bit Addressing
Second Operand #imm24 WHL rg rg' First Operand WHL (MOVG) (ADDG) (SUBG) rg MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG MOVG INCG DECG PUSH POP saddrg !!addr24 mem1 [%saddrg] SP MOVG (MOVG) (MOVG) MOVG MOVG MOVG INCG DECG MOVG MOVG (MOVG) MOVG MOVG MOVG saddrg !!addr24 mem1 [%saddrg] SP None
Note
Note Either the second operand is not used, or the second operand is not an operand address.
60
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
(4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 12-4. Instruction List by Bit Manipulation Instruction Addressing
Second Operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit First Operand CY !addr16.bit !!addr24.bit MOV1 AND1 OR1 XOR1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit MOV1 NOT1 SET1 CLR1 BF BT BTCLR BFSET /saddr.bit /sfr. bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 OR1 NOT1 SET1 CLR1 None
Note
Note Either the second operand is not used, or the second operand is not an operand address.
Data Sheet U11725EJ2V0DS00
61
PD784214,784215,784216,784214Y,784215Y,784216Y
(5) Call and return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 12-5. Instruction List by Call and Return/Branch Instruction Addressing
Operand of Instruction Address Basic instruction BC BR
Note
$addr20 $!addr20 !addr16 !!addr20
rp
rg
[rp]
[rg]
!addr11 [addr5]
RBn
None
CALL BR
CALL BR RETCS RETCSB
CALL BR
CALL BR
CALL BR
CALL BR
CALL BR
CALLF
CALLF
BRKCS BRK RET RETI RETB
Compound instruction
BF BT BTCLR BFSET DBNZ
Note The operands of BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as that of BC. (6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS
62
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
13. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD AVDD AVSS AVREF0 AVREF1 Input voltage VI1 VI2 Analog input voltage Output voltage Output current, low VAN VO IOL Per pin Total of P2, P4 to P8 Total of P0, P3, P9, P10, P12, P13 Output current, high IOH Per pin Total of P2, P4 to P8 Total of P0, P3, P9, P10, P12, P13 Operating ambient temperature Storage temperature TA A/D converter reference voltage input D/A converter reference voltage input Other than P90 to P95 P90 to P95 Analog input pin N-ch open drain Conditions Ratings -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to VSS + 0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +12 AVSS - 0.3 to AVREF0 + 0.3 -0.3 to VDD + 0.3 15 75 75 -10 -50 -50 -40 to +85 Unit V V V V V V V V V mA mA mA mA mA mA C C
Tstg
-65 to +150
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Data Sheet U11725EJ2V0DS00
63
PD784214,784215,784216,784214Y,784215Y,784216Y
Operating Conditions * Operating ambient temperature (TA): -40 to +85C * Power supply voltage and clock cycle time: see Figure 13-1 Figure 13-1. Power Supply Voltage and Clock Cycle Time
600
500
Clock Cycle Time tCYK [ns]
400
320 300
Guaranteed operating range
200 160 100 80
0 0 1 2 2.2 2.7 3 4 4.5 5 5.5 6
Supply Voltage [V]
CAPACITANCE (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance Symbol CI f = 1 MHz Unmeasured pins Output capacitance CO returned to 0 V. Conditions Other than Port 9 Port 9 Other than Port 9 Port 9 I/O capacitance CIO Other than Port 9 Port 9 MIN. TYP. MAX. 15 20 15 20 15 20 Unit pF pF pF pF pF pF
64
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
Main System Clock Oscillator Characteristics (TA = -40 to +85C)
Resonator Recommended Circuit Ceramic resonator or crystal resonator Parameter Oscillation frequency (fX) X2 X1 VSS 2.7 V VDD < 4.5 V 2 6.25 Test Conditions 4.5 V VDD 5.5 V MIN. 2 TYP. MAX. 12.5 Unit MHz
2.2 V VDD < 2.7 V
2
3
External clock X2 X1
X1 input frequency (fX)
4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V
2 2 2 15
25 12.5 6.25 250
MHz
PD74HCU04
X1 input high/lowlevel width (tWXH, tWXL) X1 input rising/ falling time (tXR, tXF) 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V
ns
0 0 0
5 10 20
ns
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always keep the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern in which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched back to the main system clock after the oscillation stabilization time is secured by the program. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U11725EJ2V0DS00
65
PD784214,784215,784216,784214Y,784215Y,784216Y
Subsystem Clock Oscillator Characteristics (TA = -40 to +85C)
Resonator Recommended Circuit Crystal resonator VSS XT2 XT1 Parameter Oscillation frequency (fXT) Test Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz
Oscillation stabilization timeNote
4.5 V VDD 5.5 V 2.2 V VDD < 4.5 V
1.2
2
s
10
External clock XT2 XT1
XT1 input frequency (fXT)
32
35
kHz
PD74HCU04
XT1 input high/lowlevel width (tXTH, tXTL)
5
15
s
Note Time required to stabilize oscillation after VDD reaches oscillator voltage MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always keep the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern in which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched back to the main system clock after the oscillation stabilization time is secured by the program. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
66
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
DC Characteristics (TA = -40 to +85C, VDD = AVDD = 2.2 to 5.5 V, VSS = AVSS = 0 V) (1/2)
Parameter Input voltage, low Symbol VIL1 VIL2 Note 1 Total of P00 to P06, P20, P22, P33, P34, P70, P72, P100 to P103, RESET P90 to P95 (N-ch open drain) Total of P10 to P17, P130, P131 Total of X1, X2, XT1, XT2 P25, P27 Note 1 Total of P00 to P06, P20, P22, P33, P34, P70, P72, P100 to P103, RESET P90 to P95 (N-ch open drain) Total of P10 to P17, P130, P131 Total of X1, X2, XT1, XT2 P25, P27 For pins other than P40 to VDD = 4.5 to 5.5 V P47, P50 to P57, P90 to P95 IOL = 1.6 mANote 2 Total of P40 to P47, P50 to P57 IOL = 8 mANote 2 VDD = 4.5 to 5.5 V Condition MIN. 0 0 TYP. MAX. 0.3VDD 0.2VDD Unit V V
VIL3 VIL4 VIL5 VIL6 Input voltage, high VIH1 VIH2
0 0 0 0 0.7VDD 0.8VDD
0.3VDD 0.3VDD 0.2VDD 0.3VDD VDD VDD
V V V V V V
VIH3 VIH4 VIH5 VIH6 Output voltage, low VOL1
0.7VDD 0.7VDD 0.8VDD 0.7VDD
12 VDD VDD VDD 0.4
V V V V V
1.0
V
P90 to P95 IOL = 15 mANote 2 VDD = 4.5 to 5.5 V VOL2 Output voltage, high VOH1 IOL = 400 IOH = -1
0.8
2.0 0.5
V V V V
ANote 2
VDD = 4.5 to 5.5 V VDD-1.0 VDD-0.5 Except X1, X2, XT1, XT2 X1, X2, XT1, XT2
mANote 2
IOL = -100 Input leakage current, low ILIL1 VIN = 0 V
ANote 2
-3
A A A A A A
ILIL2 Input leakage current, high ILIH1 VIN = VDD
-20 3
Except X1, X2, XT1, XT2 X1, X2, XT1, XT2
ILIH2 Output leakage current, low Output leakage current, high ILOL1 ILOH1 VOUT = 0 V VOUT = VDD
20 -3 3
Notes 1. P21, P23, P24, P26, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P80 to P87, P120 to P127 2. Per pin
Data Sheet U11725EJ2V0DS00
67
PD784214,784215,784216,784214Y,784215Y,784216Y
DC Characteristics (TA = -40 to +85C, VDD = AVDD = 2.2 to 5.5 V, VSS = AVSS = 0 V) (2/2)
Parameter Supply current Symbol IDD1 Operation mode Condition fXX = 12.5 MHz fXX = 6 MHz, 2.7 V VDD 3.3 V fXX = 3 MHz, 2.2 V VDD < 2.7 V IDD2 HALT mode fXX = 12.5 MHz fXX = 6 MHz, 2.7 V VDD 3.3 V fXX = 3 MHz, 2.2 V VDD < 2.7 V IDD3 IDLE mode fXX = 12.5 MHz fXX = 6 MHz, 2.7 V VDD 3.3 V fXX = 3 MHz, 2.2 V VDD < 2.7 V IDD4 Operation mode
Note
MIN.
TYP. 20 8 4 8 3 1.3 1 0.5 0.3 100 55 50 80 40 35 75 35 30
MAX. 40 17 8 20 8 3.5 2.5 1.3 0.9 200 110 100 160 80 70 150 70 60 5.5
Unit mA mA mA mA mA mA mA mA mA
fXX = 32 kHz fXX = 32 kHz, 2.7 V VDD 3.3 V fXX = 32 kHz, 2.2 V VDD < 2.7 V
A A A A A A A A A
V
IDD5
HALT mode
Note
fXX = 32 kHz fXX = 32 kHz, 2.7 V VDD 3.3 V fXX = 32 kHz, 2.2 V VDD < 2.7 V
IDD6
IDLE mode Note
fXX = 32 kHz fXX = 32 kHz, 2.7 V VDD 3.3 V fXX = 32 kHz, 2.2 V VDD < 2.7 V
Data retention voltage Data retention current
VDDDR IDDDR
HALT, IDLE modes STOP mode VDD = 2.2 V VDD = 4.5 to 5.5 V
2.2 2 10 10 30
10 50 100
A A
k
Pull-up resistor
RL
VIN = 0 V
Note When main system clock is stopped Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
68
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
AC Characteristics (TA = -40 to +85C, VDD = AVDD = 2.2 to 5.5 V, VSS = AVSS = 0 V) (1) Read/write operation (1/2)
Parameter Cycle time Symbol tCYK Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V Address setup time (to ASTB) tSAST VDD = 5.0 V VDD = 3.0 V Address hold time (from ASTB) tHSTLA VDD = 5.0 V VDD = 3.0 V ASTB high-level width tWSTH VDD = 5.0 V VDD = 3.0 V Address hold time (from RD) tHRA VDD = 5.0 V VDD = 3.0 V RD delay time from address tDAR VDD = 5.0 V VDD = 3.0 V Address float time (from RD) Data input time from address tFRA tDAID VDD = 5.0 V VDD = 3.0 V Data input time from ASTB tDSTID VDD = 5.0 V VDD = 3.0 V Data input time from RD tDRID VDD = 5.0 V VDD = 3.0 V RD delay time from ASTB tDSTR VDD = 5.0 V VDD = 3.0 V Data hold time (from RD) Address active time from RD tHRID tDRA VDD = 5.0 V VDD = 3.0 V ASTB delay time from RD tDRST VDD = 5.0 V VDD = 3.0 V RD low-level width tWRL VDD = 5.0 V VDD = 3.0 V 0.5T - 2 0.5T - 12 0.5T - 9 0.5T - 9 (1.5 + n) T - 25 (1.5 + n) T - 30 (2.5 + a + n) T - 37 (2.5 + a + n) T - 52 (2 + n) T - 35 (2 + n) T - 50 (1.5 + n) T - 40 (1.5 + n) T - 50 0.5T - 9 0.5T - 9 31 71 0 38 68 31 71 95 210 (0.5 + a) T - 11 (0.5 + a) T - 15 0.5T - 19 0.5T - 24 (0.5 + a) T - 17 (0.5 + a) T - 40 0.5T - 14 0.5T - 14 (1 + a) T - 24 (1 + a) T - 24 MIN. 80 160 320 29 65 21 56 23 40 26 66 56 136 0 403 828 285 590 240 510 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remark T: tCYK = 1/fXX (fXX: main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n 0)
Data Sheet U11725EJ2V0DS00
69
PD784214,784215,784216,784214Y,784215Y,784216Y
AC Characteristics (1) Read/write operation (2/2)
Parameter WR delay time from address Symbol tDAW Conditions VDD = 5.0 V VDD = 3.0 V Address hold time (from WR) tHWA VDD = 5.0 V VDD = 3.0 V Data output delay time from ASTB Data output delay time WR tDWOD tDSTOD VDD = 5.0 V VDD = 3.0 V 10 MIN. (1 + a) T - 24 (1 + a) T - 24 0.5T - 14 0.5T - 14 0.5T + 15 0.5T + 20 62 TYP. MAX. Unit ns ns ns ns ns ns ns
WR delay time from ASTB
tDSTW
VDD = 5.0 V VDD = 3.0 V
0.5T - 9 0.5T - 9 (1.5 + n) T - 20 (1.5 + n) T - 25 0.5T - 14 0.5T - 14 0.5T - 9 0.5T - 9 (1.5 + n) T - 25 (1.5 + n) T - 30
ns ns ns ns ns ns ns ns ns ns
Data setup time (to WR)
tSODWR
VDD = 5.0 V VDD = 3.0 V
Data hold time (from WR)
tHWOD
VDD = 5.0 V VDD = 3.0 V
ASTB delay time (from WR)
tDWST
VDD = 5.0 V VDD = 3.0 V
WD low-level width
tWWL
VDD = 5.0 V VDD = 3.0 V
Remark T: tCYK = 1/fXX (fXX: main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n 0)
70
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
AC Characteristics (2) External wait timing
Parameter WAIT input time from address Symbol tDAWT Conditions VDD = 5.0 V VDD = 3.0 V WAIT input time from ASTB tDSTWT VDD = 5.0 V VDD = 3.0 V WAIT hold time from ASTB tHSTWT VDD = 5.0 V VDD = 3.0 V WAIT delay time from ASTB tDSTWTH VDD = 5.0 V VDD = 3.0 V WAIT input time from RD tDRWTL VDD = 5.0 V VDD = 3.0 V WAIT hold time from RD tHRWT VDD = 5.0 V VDD = 3.0 V WAIT delay time from RD tDRWTH VDD = 5.0 V VDD = 3.0 V Data input time from WAIT tDWTID VDD = 5.0 V VDD = 3.0 V RD delay time from WAIT tDWTR VDD = 5.0 V VDD = 3.0 V WR delay time from WAIT tDWTW VDD = 5.0 V VDD = 3.0 V WAIT input time from WR tDWWTL VDD = 5.0 V VDD = 3.0 V WAIT hold time from WR tHWWT VDD = 5.0 V VDD = 3.0 V WAIT delay time from WR tDWWTH VDD = 5.0 V VDD = 3.0 V nT + 5 nT + 10 (1 + n) T - 40 (1 + n) T - 60 0.5T 0.5T 0.5T 0.5T T - 40 T - 60 nT + 5 nT + 10 (1 + n) T - 40 (1 + n) T - 60 0.5T - 5 0.5T - 10 (0.5 + n) T + 5 (0.5 + n) T + 10 (1.5 + n) T - 40 (1.5 + n) T - 60 T - 40 T - 60 MIN. TYP. MAX. (2 + a) T - 40 (2 + a) T - 60 1.5T - 40 1.5T - 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remark T: tCYK = 1/fXX (fXX: main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n 0)
Data Sheet U11725EJ2V0DS00
71
PD784214,784215,784216,784214Y,784215Y,784216Y
Serial Operation (TA = -40 to +85C, VDD = AVDD = 2.2 to 5.5 V, VSS = AVSS = 0 V) (a) 3-wire serial I/O mode (SCK: internal clock output)
Parameter Serial clock cycle time (SCK) Symbol tKCY1 Conditions 2.7 V VDD 5.5 V MIN. 800 3200 Serial clock high/low-level width (SCK) SI setup time (to SCK) tKH1, tKL1 tSIK1 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V 350 1500 10 30 SI hold time (from SCK) SO output delay time (from SCK) tKSI1 tKSO1 40 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns
(b) 3-wire serial I/O mode (SCK: external clock input)
Parameter Serial clock cycle time (SCK) Symbol tKCY2 Conditions 2.7 V VDD 5.5 V MIN. 800 3200 Serial clock high/low-level width (SCK) SI setup time (to SCK) tKH2, tKL2 tSIK2 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V 400 1600 10 30 SI hold time (from SCK) SO output delay time (from SCK) tKSI2 tKSO2 40 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns
(c) UART mode
Parameter ASCK cycle time Symbol tKCY3 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MIN. 417 833 1667 ASCK high/low-level width tKH3, tKL3 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 208 416 833 TYP. MAX. Unit ns ns ns ns ns ns
72
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
(d) I2C bus mode (PD784216Y Subseries only)
Parameter Symbol MIN. SCL0 clock frequency Bus free time (between stop and start conditions) Hold time Note 1 Low-level width of SCL0 clock High-level width of SCL0 clock Setup time of start/restart conditions Data hold time When using CBUScompatible master When using I2C bus tSU : DAT tR 0 Note 2 250 -- -- -- 1000 0 Note 2 100 Note 4 20 + 0.1Cb
Note 5
Standard Mode MAX. 100 --
High-Speed Mode MIN. 0 1.3 MAX. 400 --
Unit
fCLK tBUF
0 4.7
kHz
s s s s s s s
ns ns
tHD : STA tLOW tHIGH tSU : STA
4.0 4.7 4.0 4.7
-- -- -- --
0.6 1.3 0.6 0.6
-- -- -- --
tHD : DAT
5.0
--
--
--
0.9 Note 3 -- 300
Data setup time Rising time of SDA0 and SCL0 signals Falling time of SDA0 and SCL0 signals Setup time of stop condition Pulse width of spike restricted by input filter Load capacitance of each bus line
tF
--
300
20 + 0.1Cb Note 5
300
ns
tSU : STO tSP
4.0 --
-- --
0.6 0
-- 50
s
ns
Cb
--
400
--
400
pF
Notes 1. For the start condition, the first clock pulse is generated after the hold time. 2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal SDA0 signal (on VIHmin.) with at least 300 ns of hold time. 3. If the device does not extend the SCL0 signal low hold time (tLOW), only maximum data hold time tHD : DAT needs to be satisfied. 4. The high- speed mode I2C bus can be used in a standard mode I2C bus system. In this case, the conditions described below must be satisfied. * If the device does not extend the SCL0 signal low state hold time tSU : DAT 250 ns * If the device extends the SCL0 signal low state hold time Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU : DAT = 1250 ns by standard mode I2C bus specification) 5. Cb : total capacitance per one bus line (unit : pF)
Data Sheet U11725EJ2V0DS00
73
PD784214,784215,784216,784214Y,784215Y,784216Y
Other Operations (TA = -40 to +85C, VDD = AVDD = 2.2 to 5.5 V, VSS = AVSS = 0 V)
Parameter NMI high/low-level width Symbol tWNIL tWNIH tWITL tWITH tWRSL tWRSH INTP0 to INTP6 Conditions MIN. 10 TYP. MAX. Unit
s s s
INTP input high/low-level width
10
RESET high/low-level width
10
Clock Output Operation (TA = -40 to +85C, VDD = AVDD = 2.2 to 5.5 V, VSS = AVSS = 0 V)
Parameter PCL cycle time PCL high/low-level width Symbol tCYCL tCLL tCLH tCLR tCLF Conditions VDD = 4.5 to 5.5 V, nT VDD = 4.5 to 5.5 V, 0.5T - 10 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V MIN. 80 30 TYP. MAX. 31250 15615 Unit ns ns
PCL rising/falling time
5 10 20
ns ns ns
Remark T: tCYK = 1/fXX (fXX: main system clock frequency) n: Divided frequency ratio set by software in the CPU * When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128 * When using the subsystem clock: n = 1
74
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
A/D Converter Characteristics (TA = -40 to +85C, VDD = AVDD = 2.2 to 5.5 V, VSS = AVSS = 0 V)
Parameter Resolution Total error
Note
Symbol
Conditions
MIN. 8
TYP. 8
MAX. 8 1.2 1.6
Unit bit % %
2.7 V AVREF0 AVDD 2.2 V AVREF0 < 2.7 V (only when AVREF0 = AVDD)
Conversion time Sampling time Analog input voltage Reference voltage Resistance between AVREF0 and AVSS
tCONV tSAMP VIAN AVREF0 RAVREF0
14 24/fXX AVSS 2.2 29.4
144
s s
AVREF0 AVDD
V V k
Note Quantization error (1/2 LSB) is not included. Remark fXX: Main system clock frequency D/A Converter Characteristics (TA = -40 to +85C, VDD = AVDD = 2.2 to 5.5 V, VSS = AVSS = 0 V)
Parameter Resolution Total error R = 2 M, 2.2 V < AVREF1 5.5 V R = 4 M, 2.2 V < AVREF1 5.5 V R = 10 M, 2.2 V < AVREF1 5.5 V Settling time Load conditions: C = 30 pF 4.5 V AVREF1 5.5 V 2.7 V AVREF1 < 4.5 V 2.2 V AVREF1 < 2.7 V Output resistance Reference voltage AVREF1 current RO AVREF1 AIREF1 For only 1 channel DACS0, 1 = 55H 2.2 5.3 VDD 2.5 Symbol Conditions MIN. 8 TYP. 8 MAX. 8 1.2 0.8 0.6 10 15 20 Unit bit % % %
s s s
k V mA
Data Sheet U11725EJ2V0DS00
75
PD784214,784215,784216,784214Y,784215Y,784216Y
Data Retention Characteristics (TA = -40 to +85C, VDD = AVDD = 2.2 to 5.5 V, VSS = AVSS = 0 V)
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode VDDDR = +4.5 to 5.5 V VDDDR = +2.5 V VDD rising time VDD falling time VDD hold time (from STOP mode setting) STOP release signal input time tRVD tFVD tHVD 200 200 0 Conditions MIN. 2.2 10 2 TYP. MAX. 5.5 50 10 Unit V
A A s s
ms
tDREL Crystal resonator Ceramic resonator
0 30 5 0 0.9VDDDR 0.1VDDDR VDDDR
ms ms ms V V
Oscillation stabilization wait time tWAIT
Low-level input voltage High-level input voltage
VIL VIH
RESET, P00/INTP0 to P06/INTP6
AC Timing Test Points
VDD - 1 V
0.8VDD or 2.2 V Test Points 0.8 V
0.8VDD or 2.2 V 0.8 V
0.45 V
76
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
Timing Wave Form (1) Read operation
(CLK) tCYK A0-A7 (Output)
Lower address
Lower address
A8-A19 (Output) tDAID
Higher address tHRA tDRA Hi-Z Data (Input) tHRID tFRA Hi-Z
Higher address
tDSTID AD0-AD7 (Input/Output) Hi-Z Lower address (Output) tSAST ASTB (Output) tHSTLA
Lower address (Output)
tWSTH tDSTR tDAR tDRID tWRL tDRWTL tDAWT tDRWTH tHRWT tDWTR tDWTID tDRST
RD (Output)
WAIT (Input) tDSTWT tDSTWTH tHSTWT
Remark The signal is output from pins A0 to A7, when P80 to P87 are unused.
Data Sheet U11725EJ2V0DS00
77
PD784214,784215,784216,784214Y,784215Y,784216Y
(2) Write operation
(CLK) tCYK A0-A7 (Output)
Lower address
Lower address
A8-A19 (Output) tDAID
Higher address tHWA tDAW Hi-Z Data (Output) tHWOD tFRA tSODWR Hi-Z
Higher address
tDSTOD AD0-AD7 (Output) Hi-Z Lower address (Output) tSAST ASTB (Output) tHSTLA
Lower address (Output)
tWSTH tDSTW tDAW tDWOD tWWL tDWWTL tDAWT tDWWTH tHWWT tDWTW tDWTID tDWST
WR (Output)
WAIT (Input) tDSTWT tDSTWTH tHSTWT
Remark The signal is output from pins A0 to A7, when P80 to P87 are unused.
78
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
Serial Operation (1) 3-wire serial I/O mode
tKCY1, 2 tKH1, 2 tKL1, 2 SCK tKSO1, 2 tKSI1, 2 tSIK1, 2 SI/SO
(2) UART mode
tKCY3 tKH3 ASCK tKL3
(3) I2C bus mode (PD784216Y Subseries only)
tR SCL0 tHD : DAT tHD : STA tF
tHIGH tSU : DAT
tSU : STA
tHD : STA
tSP
tSU : STO
SDA0 tBUF Stop condition Start condition Restart condition Stop condition
Data Sheet U11725EJ2V0DS00
79
PD784214,784215,784216,784214Y,784215Y,784216Y
Clock Output Timing
tCLH
tCLL
CLKOUT tCLR tCYCL tCLF
Interrupt Input Timing
tWNIH
tWNIL
NMI
tWITH
tWITL
INTP0 to INTP6
Reset Input Timing
tWRSH
tWRSL
RESET
80
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
Clock Timing
tWXH
tWXL
X1 tXR 1/fX tXF
tXTH
tXTL
XT1
1/fXT
Data Retention Characteristics
STOP mode setting
VDD tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
NMI (Clearing by falling edge)
NMI (Clearing by rising edge)
Data Sheet U11725EJ2V0DS00
81
PD784214,784215,784216,784214Y,784215Y,784216Y
14. PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A B
75 76
51 50
detail of lead end S CD Q R
100 1
26 25
F G P H I
M
J K S
N
S L M
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 3 +7 -3 1.60 MAX. S100GC-50-8EU-1
Remark The external dimensions and material of the ES version are the same as those of the mass-produced version.
82
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
100-PIN PLASTIC QFP (14x20)
A B
80 81
51 50
detail of lead end S CD Q R
100 1
31 30
F G H I
M
J
P
K S N S L M
NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 0.8 0.6 0.300.10 0.15 0.65 (T.P.) 1.80.2 0.80.2 0.15+0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX.
P100GF-65-3BA1-4
Remark The external dimensions and material of the ES version are the same as those of the mass-produced version.
Data Sheet U11725EJ2V0DS00
83
PD784214,784215,784216,784214Y,784215Y,784216Y
15. RECOMMENDED SOLDERING CONDITIONS
The PD784216 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 15-1. Soldering Conditions for Surface Mount Type (1) PD784214GC-xxx-8EU : 100-pin plastic LQFP (Fine pitch) (14 x 14 mm)
PD784215GC-xxx-8EU : 100-pin plastic LQFP (Fine pitch) (14 x 14 mm) PD784216GC-xxx-8EU : 100-pin plastic LQFP (Fine pitch) (14 x 14 mm) PD784214YGC-xxx-8EU: 100-pin plastic LQFP (Fine pitch) (14 x 14 mm) PD784215YGC-xxx-8EU: 100-pin plastic LQFP (Fine pitch) (14 x 14 mm) PD784216YGC-xxx-8EU: 100-pin plastic LQFP (Fine pitch) (14 x 14 mm)
Recommended Condition Symbol IR35-00-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235C, Time: 30 sec. Max. (at 210C or higher), Count: two times or less Package peak temperature: 215C, Time: 40 sec. Max. (at 200C or higher), Count: two times or less Pin temperature: 300C Max., Time: 3 sec. Max. (per pin row)
VPS
VP15-00-2
Partial heating
--
Caution
Do not use different soldering methods together (except for partial heating).
(2) PD784214GF-xxx-3BA : 100-pin plastic QFP (14 x 20 mm)
PD784215GF-xxx-3BA : 100-pin plastic QFP (14 x 20 mm) PD784216GF-xxx-3BA : 100-pin plastic QFP (14 x 20 mm) PD784214YGF-xxx-3BA : 100-pin plastic QFP (14 x 20 mm) PD784215YGF-xxx-3BA : 100-pin plastic QFP (14 x 20 mm) PD784216YGF-xxx-3BA : 100-pin plastic QFP (14 x 20 mm)
Recommended Condition Symbol IR35-00-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235C, Time: 30 sec. Max. (at 210C or higher), Count: two times or less Package peak temperature: 215C, Time: 40 sec. Max. (at 200C or higher), Count: two times or less
VPS
VP15-00-2
Wave soldering
Solder bath temperature: 260C Max., Time: 10 sec. Max., Count: once, Preheating temperature: 120C Max. (package surface temperature) Pin temperature: 300C Max., Time: 3 sec. Max. (per pin row)
WS60-00-1
Partial heating
--
Caution
Do not use different soldering methods together (except for partial heating).
84
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for system development using the PD784216. Also refer to (5) Cautions on Using Development Tools. (1) Language Processing Software
RA78K4 CC78K4 DF784218 CC78K4-L Assembler package common to 78K/IV Series C compiler package common to 78K/IV Series Device file common to PD784216, 784216Y Subseries C compiler library source file common to 78K/IV Series
(2) Flash Memory Writing Tools
Flashpro II (Model number: FL-PR2), Flashpro III (Model number: FL-PR3, PG-FP3) FA-100GF Dedicated flash programmer for microcontroller incorporating flash memory
Adapter for writing 100-pin plastic QFP (GF-3BA type) flash memory. Connection must be performed depending on the target product. Adapter for writing 100-pin plastic LQFP (GC-8EU type) flash memory. Connection must be performed depending on the target product.
FA-100GC
Flashpro II controller, Flashpro III controller
Control program that runs on a personal computer and is attached to Flashpro II, Flashpro III. Operates on WindowsTM95, etc.
(3) Debugging Tools * When IE-78K4-NS in-circuit emulator is used
IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C IE-70000-CD-IF-A Note In-circuit emulator common to 78K/IV Series Power supply unit for IE-78K4-NS Interface adapter used when PC-9800 series PC (except notebook type) is used as host machine (C bus supported) PC card and cable when PC-9800 series notebook PC is used as host machine (PCMCIA socket supported) Interface adapter when using IBM PC/ATTM compatibles as host machine (ISA bus supported) Interface adapter when using PC that incorporates PCI bus as host machine Emulation board to emulate PD784216, 784216Y Subseries Emulation probe for 100-pin plastic QFP (GF-3BA type) Emulation probe for 100-pin plastic LQFP (GC-8EU type) Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) Conversion adapter to connect the NP-100GC and a target system board on which a 100pin plastic LQFP (GC-8EU type) can be mounted Integrated debugger for IE-78K4-NS System simulator common to 78K/IV Series Device file common to PD784216, 784216Y Subseries
IE-70000-PC-IF-C IE-70000-PCI-IF Note IE-784225-NS-EM1 NP-100GF NP-100GC EV-9200GF-100 TGC-100SDW
ID78K4-NS SM78K4 DF784218
Note Under development
Data Sheet U11725EJ2V0DS00
85
PD784214,784215,784216,784214Y,784215Y,784216Y
* When IE-784000-R in-circuit emulator is used
In-circuit emulator common to 78K/IV Series Interface adapter used when PC-9800 series PC (except notebook type) is used as host machine (C bus supported) Interface adapter when using IBM PC/AT and compatibles as host machine (ISA bus supported) Interface adapter when using PC that incorporates PCI bus as host machine Interface adapter and cable used when EWS is used as host machine Emulation board to emulate PD784216, 784216Y Subseries
IE-784000-R IE-70000-98-IF-C
IE-70000-PC-IF-C IE-70000-PCI-IF Note IE-78000-R-SV3 IE-784225-NS-EM1 IE-784216-R-EM1 IE-784000-R-EM IE-78K4-R-EX3
Emulation board common to 78K/IV Series Emulation probe conversion board necessary when using IE-784225-NS-EM1 on IE784000-R. Not necessary when IE-784216-R-EM1 is used. Emulation probe for 100-pin plastic QFP (GF-3BA type) Emulation probe for 100-pin plastic LQFP (GC-8EU type) Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) Conversion adapter to connect the NP-100GC and a target system board on which a 100pin plastic LQFP (GC-8EU type) can be mounted Integrated debugger for IE-784000-R System simulator common to 78K/IV Series Device file common to PD784216, 784216Y Subseries
EP-78064GF-R EP-78064GC-R EV-9200GF-100 TGC-100SDW
ID78K4 SM78K4 DF784218
Note Under development (4) Real-time OS
RX78K/IV MX78K4 Real-time OS for 78K/IV Series OS for 78K/IV Series
86
Data Sheet U11725EJ2V0DS00
PD784214,784215,784216,784214Y,784215Y,784216Y
(5) Cautions on Using Development Tools * The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784218. * The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784218. * The FL-PR2, FL-PR3, FA-100GF, FA-100GC, NP-100GF, and NP-100GC are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813). * The TGC-100SDW is a product made by Tokyo Eletech Corporation. * For further information, contact Daimaru Kogyo, Ltd. Tokyo Electronic Division (TEL: +81-3-3820-7112) Osaka Electronic Division (TEL: +81-6-6244-6672) * For third party development tools, see the 78K/IV Series Selection Guide (U13355E). * The host machine and OS suitable for each software are as follows:
Host Machine [OS] Software RA78K4 CC78K4 ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4 PC PC-9800 series [Windows] IBM PC/AT and compatibles [Japanese/English Windows] Note
Note
EWS HP9000 Series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] NEWSTM (RISC) [NEWS-OSTM] - -

Note
Note
Note DOS-based software
Data Sheet U11725EJ2V0DS00
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APPENDIX B. RELATED DOCUMENTS
Documents related to device
Document Name Document No. Japanese English This document U11824E U12015E - U10905E - - U10095E
PD784214, 784215, 784216, 784214Y, 784215Y, 784216Y Data Sheet PD78F4216, 78F4216Y Data Sheet PD784216, 784216Y Subseries User's Manual Hardware PD784216Y Subseries Special Function Register Table
78K/IV Series User's Manual Instructions 78K/IV Series Instruction Table 78K/IV Series Instruction Set 78K/IV Series Application Note Software Basics
U11725J U11824J U12015J U12046J U10905J U10594J U10595J U10095J
Documents related to development tool (User's Manual)
Document Name Document No. Japanese RA78K4 Assembler Package Language Operation RA78K Structured Assembler Preprocessor CC78K4 C Compiler Language Operation IE-78K4-NS IE-784000-R IE-784218-R-EM1 IE-784225-NS-EM1 EP-78064 SM78K4 System Simulator Windows Based SM78K Series System Simulator Reference External Part User Open Interface Specifications Reference Reference Reference U11162J U11334J U11743J U11571J U11572J U13356J U12903J U12155J U13742J EEU-934 U10093J U10092J English U11162E U11334E U11743E U11571E U11572E U13356E U12903E U12155E To be prepared EEU-1469 U10093E U10092E
ID78K4-NS Integrated Debugger PC Based ID78K4 Integrated Debugger Windows Based ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS based
U12796J U10440J U11960J
U12796E U10440E U11960E
Caution
The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of a document for designing.
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PD784214,784215,784216,784214Y,784215Y,784216Y
Documents related to embedded software (User's Manual)
Document Name Document No. Japanese 78K/IV Series Real-Time OS Fundamental Installation Debugger 78K/IV Series OS MX78K4 Fundamental U10603J U10604J U10364J U11779J English U10603E U10604E - -
Other documents
Document Name Document No. Japanese SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Microcontroller-Related Products by Third Parties C10535J C11531J C10983J C11892J U11416J X13769X C10535E C11531E C10983E C11892E - English
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Data Sheet U11725EJ2V0DS00
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NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
IEBus is a trademark of NEC Corporation. Windows is a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation.
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
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The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
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